musbhsdma.c revision 6bd03e7b9d0f70928f9cd793326c28e4e08ffc96
1/* 2 * MUSB OTG driver - support for Mentor's DMA controller 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2007 by Texas Instruments 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33#include <linux/device.h> 34#include <linux/interrupt.h> 35#include <linux/platform_device.h> 36#include "musb_core.h" 37#include "musbhsdma.h" 38 39static int dma_controller_start(struct dma_controller *c) 40{ 41 /* nothing to do */ 42 return 0; 43} 44 45static void dma_channel_release(struct dma_channel *channel); 46 47static int dma_controller_stop(struct dma_controller *c) 48{ 49 struct musb_dma_controller *controller = container_of(c, 50 struct musb_dma_controller, controller); 51 struct musb *musb = controller->private_data; 52 struct dma_channel *channel; 53 u8 bit; 54 55 if (controller->used_channels != 0) { 56 dev_err(musb->controller, 57 "Stopping DMA controller while channel active\n"); 58 59 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 60 if (controller->used_channels & (1 << bit)) { 61 channel = &controller->channel[bit].channel; 62 dma_channel_release(channel); 63 64 if (!controller->used_channels) 65 break; 66 } 67 } 68 } 69 70 return 0; 71} 72 73static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 74 struct musb_hw_ep *hw_ep, u8 transmit) 75{ 76 struct musb_dma_controller *controller = container_of(c, 77 struct musb_dma_controller, controller); 78 struct musb_dma_channel *musb_channel = NULL; 79 struct dma_channel *channel = NULL; 80 u8 bit; 81 82 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 83 if (!(controller->used_channels & (1 << bit))) { 84 controller->used_channels |= (1 << bit); 85 musb_channel = &(controller->channel[bit]); 86 musb_channel->controller = controller; 87 musb_channel->idx = bit; 88 musb_channel->epnum = hw_ep->epnum; 89 musb_channel->transmit = transmit; 90 channel = &(musb_channel->channel); 91 channel->private_data = musb_channel; 92 channel->status = MUSB_DMA_STATUS_FREE; 93 channel->max_len = 0x10000; 94 /* Tx => mode 1; Rx => mode 0 */ 95 channel->desired_mode = transmit; 96 channel->actual_len = 0; 97 break; 98 } 99 } 100 101 return channel; 102} 103 104static void dma_channel_release(struct dma_channel *channel) 105{ 106 struct musb_dma_channel *musb_channel = channel->private_data; 107 108 channel->actual_len = 0; 109 musb_channel->start_addr = 0; 110 musb_channel->len = 0; 111 112 musb_channel->controller->used_channels &= 113 ~(1 << musb_channel->idx); 114 115 channel->status = MUSB_DMA_STATUS_UNKNOWN; 116} 117 118static void configure_channel(struct dma_channel *channel, 119 u16 packet_sz, u8 mode, 120 dma_addr_t dma_addr, u32 len) 121{ 122 struct musb_dma_channel *musb_channel = channel->private_data; 123 struct musb_dma_controller *controller = musb_channel->controller; 124 void __iomem *mbase = controller->base; 125 u8 bchannel = musb_channel->idx; 126 u16 csr = 0; 127 128 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 129 channel, packet_sz, dma_addr, len, mode); 130 131 if (mode) { 132 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 133 BUG_ON(len < packet_sz); 134 135 if (packet_sz >= 64) { 136 csr |= MUSB_HSDMA_BURSTMODE_INCR16 137 << MUSB_HSDMA_BURSTMODE_SHIFT; 138 } else if (packet_sz >= 32) { 139 csr |= MUSB_HSDMA_BURSTMODE_INCR8 140 << MUSB_HSDMA_BURSTMODE_SHIFT; 141 } else if (packet_sz >= 16) { 142 csr |= MUSB_HSDMA_BURSTMODE_INCR4 143 << MUSB_HSDMA_BURSTMODE_SHIFT; 144 } 145 } 146 147 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 148 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 149 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 150 | (musb_channel->transmit 151 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 152 : 0); 153 154 /* address/count */ 155 musb_write_hsdma_addr(mbase, bchannel, dma_addr); 156 musb_write_hsdma_count(mbase, bchannel, len); 157 158 /* control (this should start things) */ 159 musb_writew(mbase, 160 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 161 csr); 162} 163 164static int dma_channel_program(struct dma_channel *channel, 165 u16 packet_sz, u8 mode, 166 dma_addr_t dma_addr, u32 len) 167{ 168 struct musb_dma_channel *musb_channel = channel->private_data; 169 170 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 171 musb_channel->epnum, 172 musb_channel->transmit ? "Tx" : "Rx", 173 packet_sz, dma_addr, len, mode); 174 175 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 176 channel->status == MUSB_DMA_STATUS_BUSY); 177 178 channel->actual_len = 0; 179 musb_channel->start_addr = dma_addr; 180 musb_channel->len = len; 181 musb_channel->max_packet_sz = packet_sz; 182 channel->status = MUSB_DMA_STATUS_BUSY; 183 184 if ((mode == 1) && (len >= packet_sz)) 185 configure_channel(channel, packet_sz, 1, dma_addr, len); 186 else 187 configure_channel(channel, packet_sz, 0, dma_addr, len); 188 189 return true; 190} 191 192static int dma_channel_abort(struct dma_channel *channel) 193{ 194 struct musb_dma_channel *musb_channel = channel->private_data; 195 void __iomem *mbase = musb_channel->controller->base; 196 197 u8 bchannel = musb_channel->idx; 198 int offset; 199 u16 csr; 200 201 if (channel->status == MUSB_DMA_STATUS_BUSY) { 202 if (musb_channel->transmit) { 203 offset = MUSB_EP_OFFSET(musb_channel->epnum, 204 MUSB_TXCSR); 205 206 /* 207 * The programming guide says that we must clear 208 * the DMAENAB bit before the DMAMODE bit... 209 */ 210 csr = musb_readw(mbase, offset); 211 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 212 musb_writew(mbase, offset, csr); 213 csr &= ~MUSB_TXCSR_DMAMODE; 214 musb_writew(mbase, offset, csr); 215 } else { 216 offset = MUSB_EP_OFFSET(musb_channel->epnum, 217 MUSB_RXCSR); 218 219 csr = musb_readw(mbase, offset); 220 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 221 MUSB_RXCSR_DMAENAB | 222 MUSB_RXCSR_DMAMODE); 223 musb_writew(mbase, offset, csr); 224 } 225 226 musb_writew(mbase, 227 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 228 0); 229 musb_write_hsdma_addr(mbase, bchannel, 0); 230 musb_write_hsdma_count(mbase, bchannel, 0); 231 channel->status = MUSB_DMA_STATUS_FREE; 232 } 233 234 return 0; 235} 236 237static irqreturn_t dma_controller_irq(int irq, void *private_data) 238{ 239 struct musb_dma_controller *controller = private_data; 240 struct musb *musb = controller->private_data; 241 struct musb_dma_channel *musb_channel; 242 struct dma_channel *channel; 243 244 void __iomem *mbase = controller->base; 245 246 irqreturn_t retval = IRQ_NONE; 247 248 unsigned long flags; 249 250 u8 bchannel; 251 u8 int_hsdma; 252 253 u32 addr; 254 u16 csr; 255 256 spin_lock_irqsave(&musb->lock, flags); 257 258 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 259 if (!int_hsdma) 260 goto done; 261 262#ifdef CONFIG_BLACKFIN 263 /* Clear DMA interrupt flags */ 264 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); 265#endif 266 267 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 268 if (int_hsdma & (1 << bchannel)) { 269 musb_channel = (struct musb_dma_channel *) 270 &(controller->channel[bchannel]); 271 channel = &musb_channel->channel; 272 273 csr = musb_readw(mbase, 274 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, 275 MUSB_HSDMA_CONTROL)); 276 277 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { 278 musb_channel->channel.status = 279 MUSB_DMA_STATUS_BUS_ABORT; 280 } else { 281 u8 devctl; 282 283 addr = musb_read_hsdma_addr(mbase, 284 bchannel); 285 channel->actual_len = addr 286 - musb_channel->start_addr; 287 288 DBG(2, "ch %p, 0x%x -> 0x%x (%d / %d) %s\n", 289 channel, musb_channel->start_addr, 290 addr, channel->actual_len, 291 musb_channel->len, 292 (channel->actual_len 293 < musb_channel->len) ? 294 "=> reconfig 0" : "=> complete"); 295 296 devctl = musb_readb(mbase, MUSB_DEVCTL); 297 298 channel->status = MUSB_DMA_STATUS_FREE; 299 300 /* completed */ 301 if ((devctl & MUSB_DEVCTL_HM) 302 && (musb_channel->transmit) 303 && ((channel->desired_mode == 0) 304 || (channel->actual_len & 305 (musb_channel->max_packet_sz - 1))) 306 ) { 307 u8 epnum = musb_channel->epnum; 308 int offset = MUSB_EP_OFFSET(epnum, 309 MUSB_TXCSR); 310 u16 txcsr; 311 312 /* 313 * The programming guide says that we 314 * must clear DMAENAB before DMAMODE. 315 */ 316 musb_ep_select(mbase, epnum); 317 txcsr = musb_readw(mbase, offset); 318 txcsr &= ~(MUSB_TXCSR_DMAENAB 319 | MUSB_TXCSR_AUTOSET); 320 musb_writew(mbase, offset, txcsr); 321 /* Send out the packet */ 322 txcsr &= ~MUSB_TXCSR_DMAMODE; 323 txcsr |= MUSB_TXCSR_TXPKTRDY; 324 musb_writew(mbase, offset, txcsr); 325 } 326 musb_dma_completion(musb, musb_channel->epnum, 327 musb_channel->transmit); 328 } 329 } 330 } 331 332 retval = IRQ_HANDLED; 333done: 334 spin_unlock_irqrestore(&musb->lock, flags); 335 return retval; 336} 337 338void dma_controller_destroy(struct dma_controller *c) 339{ 340 struct musb_dma_controller *controller = container_of(c, 341 struct musb_dma_controller, controller); 342 343 if (!controller) 344 return; 345 346 if (controller->irq) 347 free_irq(controller->irq, c); 348 349 kfree(controller); 350} 351 352struct dma_controller *__init 353dma_controller_create(struct musb *musb, void __iomem *base) 354{ 355 struct musb_dma_controller *controller; 356 struct device *dev = musb->controller; 357 struct platform_device *pdev = to_platform_device(dev); 358 int irq = platform_get_irq(pdev, 1); 359 360 if (irq == 0) { 361 dev_err(dev, "No DMA interrupt line!\n"); 362 return NULL; 363 } 364 365 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 366 if (!controller) 367 return NULL; 368 369 controller->channel_count = MUSB_HSDMA_CHANNELS; 370 controller->private_data = musb; 371 controller->base = base; 372 373 controller->controller.start = dma_controller_start; 374 controller->controller.stop = dma_controller_stop; 375 controller->controller.channel_alloc = dma_channel_allocate; 376 controller->controller.channel_release = dma_channel_release; 377 controller->controller.channel_program = dma_channel_program; 378 controller->controller.channel_abort = dma_channel_abort; 379 380 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, 381 dev_name(musb->controller), &controller->controller)) { 382 dev_err(dev, "request_irq %d failed!\n", irq); 383 dma_controller_destroy(&controller->controller); 384 385 return NULL; 386 } 387 388 controller->irq = irq; 389 390 return &controller->controller; 391} 392