musbhsdma.c revision 8ca47c8a7621835914c053caaec74e66147dd7dc
1/* 2 * MUSB OTG driver - support for Mentor's DMA controller 3 * 4 * Copyright 2005 Mentor Graphics Corporation 5 * Copyright (C) 2005-2007 by Texas Instruments 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 * 21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF 27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33#include <linux/device.h> 34#include <linux/interrupt.h> 35#include <linux/platform_device.h> 36#include <linux/slab.h> 37#include "musb_core.h" 38#include "musbhsdma.h" 39 40static int dma_controller_start(struct dma_controller *c) 41{ 42 /* nothing to do */ 43 return 0; 44} 45 46static void dma_channel_release(struct dma_channel *channel); 47 48static int dma_controller_stop(struct dma_controller *c) 49{ 50 struct musb_dma_controller *controller = container_of(c, 51 struct musb_dma_controller, controller); 52 struct musb *musb = controller->private_data; 53 struct dma_channel *channel; 54 u8 bit; 55 56 if (controller->used_channels != 0) { 57 dev_err(musb->controller, 58 "Stopping DMA controller while channel active\n"); 59 60 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 61 if (controller->used_channels & (1 << bit)) { 62 channel = &controller->channel[bit].channel; 63 dma_channel_release(channel); 64 65 if (!controller->used_channels) 66 break; 67 } 68 } 69 } 70 71 return 0; 72} 73 74static struct dma_channel *dma_channel_allocate(struct dma_controller *c, 75 struct musb_hw_ep *hw_ep, u8 transmit) 76{ 77 struct musb_dma_controller *controller = container_of(c, 78 struct musb_dma_controller, controller); 79 struct musb_dma_channel *musb_channel = NULL; 80 struct dma_channel *channel = NULL; 81 u8 bit; 82 83 for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) { 84 if (!(controller->used_channels & (1 << bit))) { 85 controller->used_channels |= (1 << bit); 86 musb_channel = &(controller->channel[bit]); 87 musb_channel->controller = controller; 88 musb_channel->idx = bit; 89 musb_channel->epnum = hw_ep->epnum; 90 musb_channel->transmit = transmit; 91 channel = &(musb_channel->channel); 92 channel->private_data = musb_channel; 93 channel->status = MUSB_DMA_STATUS_FREE; 94 channel->max_len = 0x10000; 95 /* Tx => mode 1; Rx => mode 0 */ 96 channel->desired_mode = transmit; 97 channel->actual_len = 0; 98 break; 99 } 100 } 101 102 return channel; 103} 104 105static void dma_channel_release(struct dma_channel *channel) 106{ 107 struct musb_dma_channel *musb_channel = channel->private_data; 108 109 channel->actual_len = 0; 110 musb_channel->start_addr = 0; 111 musb_channel->len = 0; 112 113 musb_channel->controller->used_channels &= 114 ~(1 << musb_channel->idx); 115 116 channel->status = MUSB_DMA_STATUS_UNKNOWN; 117} 118 119static void configure_channel(struct dma_channel *channel, 120 u16 packet_sz, u8 mode, 121 dma_addr_t dma_addr, u32 len) 122{ 123 struct musb_dma_channel *musb_channel = channel->private_data; 124 struct musb_dma_controller *controller = musb_channel->controller; 125 void __iomem *mbase = controller->base; 126 u8 bchannel = musb_channel->idx; 127 u16 csr = 0; 128 129 DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n", 130 channel, packet_sz, dma_addr, len, mode); 131 132 if (mode) { 133 csr |= 1 << MUSB_HSDMA_MODE1_SHIFT; 134 BUG_ON(len < packet_sz); 135 } 136 csr |= MUSB_HSDMA_BURSTMODE_INCR16 137 << MUSB_HSDMA_BURSTMODE_SHIFT; 138 139 csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT) 140 | (1 << MUSB_HSDMA_ENABLE_SHIFT) 141 | (1 << MUSB_HSDMA_IRQENABLE_SHIFT) 142 | (musb_channel->transmit 143 ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT) 144 : 0); 145 146 /* address/count */ 147 musb_write_hsdma_addr(mbase, bchannel, dma_addr); 148 musb_write_hsdma_count(mbase, bchannel, len); 149 150 /* control (this should start things) */ 151 musb_writew(mbase, 152 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 153 csr); 154} 155 156static int dma_channel_program(struct dma_channel *channel, 157 u16 packet_sz, u8 mode, 158 dma_addr_t dma_addr, u32 len) 159{ 160 struct musb_dma_channel *musb_channel = channel->private_data; 161 162 DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n", 163 musb_channel->epnum, 164 musb_channel->transmit ? "Tx" : "Rx", 165 packet_sz, dma_addr, len, mode); 166 167 BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN || 168 channel->status == MUSB_DMA_STATUS_BUSY); 169 170 channel->actual_len = 0; 171 musb_channel->start_addr = dma_addr; 172 musb_channel->len = len; 173 musb_channel->max_packet_sz = packet_sz; 174 channel->status = MUSB_DMA_STATUS_BUSY; 175 176 configure_channel(channel, packet_sz, mode, dma_addr, len); 177 178 return true; 179} 180 181static int dma_channel_abort(struct dma_channel *channel) 182{ 183 struct musb_dma_channel *musb_channel = channel->private_data; 184 void __iomem *mbase = musb_channel->controller->base; 185 186 u8 bchannel = musb_channel->idx; 187 int offset; 188 u16 csr; 189 190 if (channel->status == MUSB_DMA_STATUS_BUSY) { 191 if (musb_channel->transmit) { 192 offset = MUSB_EP_OFFSET(musb_channel->epnum, 193 MUSB_TXCSR); 194 195 /* 196 * The programming guide says that we must clear 197 * the DMAENAB bit before the DMAMODE bit... 198 */ 199 csr = musb_readw(mbase, offset); 200 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); 201 musb_writew(mbase, offset, csr); 202 csr &= ~MUSB_TXCSR_DMAMODE; 203 musb_writew(mbase, offset, csr); 204 } else { 205 offset = MUSB_EP_OFFSET(musb_channel->epnum, 206 MUSB_RXCSR); 207 208 csr = musb_readw(mbase, offset); 209 csr &= ~(MUSB_RXCSR_AUTOCLEAR | 210 MUSB_RXCSR_DMAENAB | 211 MUSB_RXCSR_DMAMODE); 212 musb_writew(mbase, offset, csr); 213 } 214 215 musb_writew(mbase, 216 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL), 217 0); 218 musb_write_hsdma_addr(mbase, bchannel, 0); 219 musb_write_hsdma_count(mbase, bchannel, 0); 220 channel->status = MUSB_DMA_STATUS_FREE; 221 } 222 223 return 0; 224} 225 226static irqreturn_t dma_controller_irq(int irq, void *private_data) 227{ 228 struct musb_dma_controller *controller = private_data; 229 struct musb *musb = controller->private_data; 230 struct musb_dma_channel *musb_channel; 231 struct dma_channel *channel; 232 233 void __iomem *mbase = controller->base; 234 235 irqreturn_t retval = IRQ_NONE; 236 237 unsigned long flags; 238 239 u8 bchannel; 240 u8 int_hsdma; 241 242 u32 addr, count; 243 u16 csr; 244 245 spin_lock_irqsave(&musb->lock, flags); 246 247 int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR); 248 249#ifdef CONFIG_BLACKFIN 250 /* Clear DMA interrupt flags */ 251 musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma); 252#endif 253 254 if (!int_hsdma) { 255 DBG(2, "spurious DMA irq\n"); 256 257 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 258 musb_channel = (struct musb_dma_channel *) 259 &(controller->channel[bchannel]); 260 channel = &musb_channel->channel; 261 if (channel->status == MUSB_DMA_STATUS_BUSY) { 262 count = musb_read_hsdma_count(mbase, bchannel); 263 264 if (count == 0) 265 int_hsdma |= (1 << bchannel); 266 } 267 } 268 269 DBG(2, "int_hsdma = 0x%x\n", int_hsdma); 270 271 if (!int_hsdma) 272 goto done; 273 } 274 275 for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) { 276 if (int_hsdma & (1 << bchannel)) { 277 musb_channel = (struct musb_dma_channel *) 278 &(controller->channel[bchannel]); 279 channel = &musb_channel->channel; 280 281 csr = musb_readw(mbase, 282 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, 283 MUSB_HSDMA_CONTROL)); 284 285 if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) { 286 musb_channel->channel.status = 287 MUSB_DMA_STATUS_BUS_ABORT; 288 } else { 289 u8 devctl; 290 291 addr = musb_read_hsdma_addr(mbase, 292 bchannel); 293 channel->actual_len = addr 294 - musb_channel->start_addr; 295 296 DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n", 297 channel, musb_channel->start_addr, 298 addr, channel->actual_len, 299 musb_channel->len, 300 (channel->actual_len 301 < musb_channel->len) ? 302 "=> reconfig 0" : "=> complete"); 303 304 devctl = musb_readb(mbase, MUSB_DEVCTL); 305 306 channel->status = MUSB_DMA_STATUS_FREE; 307 308 /* completed */ 309 if ((devctl & MUSB_DEVCTL_HM) 310 && (musb_channel->transmit) 311 && ((channel->desired_mode == 0) 312 || (channel->actual_len & 313 (musb_channel->max_packet_sz - 1))) 314 ) { 315 u8 epnum = musb_channel->epnum; 316 int offset = MUSB_EP_OFFSET(epnum, 317 MUSB_TXCSR); 318 u16 txcsr; 319 320 /* 321 * The programming guide says that we 322 * must clear DMAENAB before DMAMODE. 323 */ 324 musb_ep_select(mbase, epnum); 325 txcsr = musb_readw(mbase, offset); 326 txcsr &= ~(MUSB_TXCSR_DMAENAB 327 | MUSB_TXCSR_AUTOSET); 328 musb_writew(mbase, offset, txcsr); 329 /* Send out the packet */ 330 txcsr &= ~MUSB_TXCSR_DMAMODE; 331 txcsr |= MUSB_TXCSR_TXPKTRDY; 332 musb_writew(mbase, offset, txcsr); 333 } 334 musb_dma_completion(musb, musb_channel->epnum, 335 musb_channel->transmit); 336 } 337 } 338 } 339 340 retval = IRQ_HANDLED; 341done: 342 spin_unlock_irqrestore(&musb->lock, flags); 343 return retval; 344} 345 346void dma_controller_destroy(struct dma_controller *c) 347{ 348 struct musb_dma_controller *controller = container_of(c, 349 struct musb_dma_controller, controller); 350 351 if (!controller) 352 return; 353 354 if (controller->irq) 355 free_irq(controller->irq, c); 356 357 kfree(controller); 358} 359 360struct dma_controller *__init 361dma_controller_create(struct musb *musb, void __iomem *base) 362{ 363 struct musb_dma_controller *controller; 364 struct device *dev = musb->controller; 365 struct platform_device *pdev = to_platform_device(dev); 366 int irq = platform_get_irq(pdev, 1); 367 368 if (irq == 0) { 369 dev_err(dev, "No DMA interrupt line!\n"); 370 return NULL; 371 } 372 373 controller = kzalloc(sizeof(*controller), GFP_KERNEL); 374 if (!controller) 375 return NULL; 376 377 controller->channel_count = MUSB_HSDMA_CHANNELS; 378 controller->private_data = musb; 379 controller->base = base; 380 381 controller->controller.start = dma_controller_start; 382 controller->controller.stop = dma_controller_stop; 383 controller->controller.channel_alloc = dma_channel_allocate; 384 controller->controller.channel_release = dma_channel_release; 385 controller->controller.channel_program = dma_channel_program; 386 controller->controller.channel_abort = dma_channel_abort; 387 388 if (request_irq(irq, dma_controller_irq, IRQF_DISABLED, 389 dev_name(musb->controller), &controller->controller)) { 390 dev_err(dev, "request_irq %d failed!\n", irq); 391 dma_controller_destroy(&controller->controller); 392 393 return NULL; 394 } 395 396 controller->irq = irq; 397 398 return &controller->controller; 399} 400