1/* 2 * TUSB6010 USB 2.0 OTG Dual Role controller OMAP DMA interface 3 * 4 * Copyright (C) 2006 Nokia Corporation 5 * Tony Lindgren <tony@atomide.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/module.h> 12#include <linux/kernel.h> 13#include <linux/errno.h> 14#include <linux/init.h> 15#include <linux/usb.h> 16#include <linux/platform_device.h> 17#include <linux/dma-mapping.h> 18#include <linux/slab.h> 19#include <plat/dma.h> 20#include <plat/mux.h> 21 22#include "musb_core.h" 23#include "tusb6010.h" 24 25#define to_chdat(c) ((struct tusb_omap_dma_ch *)(c)->private_data) 26 27#define MAX_DMAREQ 5 /* REVISIT: Really 6, but req5 not OK */ 28 29struct tusb_omap_dma_ch { 30 struct musb *musb; 31 void __iomem *tbase; 32 unsigned long phys_offset; 33 int epnum; 34 u8 tx; 35 struct musb_hw_ep *hw_ep; 36 37 int ch; 38 s8 dmareq; 39 s8 sync_dev; 40 41 struct tusb_omap_dma *tusb_dma; 42 43 dma_addr_t dma_addr; 44 45 u32 len; 46 u16 packet_sz; 47 u16 transfer_packet_sz; 48 u32 transfer_len; 49 u32 completed_len; 50}; 51 52struct tusb_omap_dma { 53 struct dma_controller controller; 54 struct musb *musb; 55 void __iomem *tbase; 56 57 int ch; 58 s8 dmareq; 59 s8 sync_dev; 60 unsigned multichannel:1; 61}; 62 63static int tusb_omap_dma_start(struct dma_controller *c) 64{ 65 struct tusb_omap_dma *tusb_dma; 66 67 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 68 69 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 70 71 return 0; 72} 73 74static int tusb_omap_dma_stop(struct dma_controller *c) 75{ 76 struct tusb_omap_dma *tusb_dma; 77 78 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 79 80 /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */ 81 82 return 0; 83} 84 85/* 86 * Allocate dmareq0 to the current channel unless it's already taken 87 */ 88static inline int tusb_omap_use_shared_dmareq(struct tusb_omap_dma_ch *chdat) 89{ 90 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 91 92 if (reg != 0) { 93 dev_dbg(chdat->musb->controller, "ep%i dmareq0 is busy for ep%i\n", 94 chdat->epnum, reg & 0xf); 95 return -EAGAIN; 96 } 97 98 if (chdat->tx) 99 reg = (1 << 4) | chdat->epnum; 100 else 101 reg = chdat->epnum; 102 103 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 104 105 return 0; 106} 107 108static inline void tusb_omap_free_shared_dmareq(struct tusb_omap_dma_ch *chdat) 109{ 110 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 111 112 if ((reg & 0xf) != chdat->epnum) { 113 printk(KERN_ERR "ep%i trying to release dmareq0 for ep%i\n", 114 chdat->epnum, reg & 0xf); 115 return; 116 } 117 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, 0); 118} 119 120/* 121 * See also musb_dma_completion in plat_uds.c and musb_g_[tx|rx]() in 122 * musb_gadget.c. 123 */ 124static void tusb_omap_dma_cb(int lch, u16 ch_status, void *data) 125{ 126 struct dma_channel *channel = (struct dma_channel *)data; 127 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 128 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 129 struct musb *musb = chdat->musb; 130 struct device *dev = musb->controller; 131 struct musb_hw_ep *hw_ep = chdat->hw_ep; 132 void __iomem *ep_conf = hw_ep->conf; 133 void __iomem *mbase = musb->mregs; 134 unsigned long remaining, flags, pio; 135 int ch; 136 137 spin_lock_irqsave(&musb->lock, flags); 138 139 if (tusb_dma->multichannel) 140 ch = chdat->ch; 141 else 142 ch = tusb_dma->ch; 143 144 if (ch_status != OMAP_DMA_BLOCK_IRQ) 145 printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status); 146 147 dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n", 148 chdat->epnum, chdat->tx ? "tx" : "rx", 149 ch, ch_status); 150 151 if (chdat->tx) 152 remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 153 else 154 remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 155 156 remaining = TUSB_EP_CONFIG_XFR_SIZE(remaining); 157 158 /* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */ 159 if (unlikely(remaining > chdat->transfer_len)) { 160 dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n", 161 chdat->tx ? "tx" : "rx", chdat->ch, 162 remaining); 163 remaining = 0; 164 } 165 166 channel->actual_len = chdat->transfer_len - remaining; 167 pio = chdat->len - channel->actual_len; 168 169 dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len); 170 171 /* Transfer remaining 1 - 31 bytes */ 172 if (pio > 0 && pio < 32) { 173 u8 *buf; 174 175 dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio); 176 buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len; 177 if (chdat->tx) { 178 dma_unmap_single(dev, chdat->dma_addr, 179 chdat->transfer_len, 180 DMA_TO_DEVICE); 181 musb_write_fifo(hw_ep, pio, buf); 182 } else { 183 dma_unmap_single(dev, chdat->dma_addr, 184 chdat->transfer_len, 185 DMA_FROM_DEVICE); 186 musb_read_fifo(hw_ep, pio, buf); 187 } 188 channel->actual_len += pio; 189 } 190 191 if (!tusb_dma->multichannel) 192 tusb_omap_free_shared_dmareq(chdat); 193 194 channel->status = MUSB_DMA_STATUS_FREE; 195 196 /* Handle only RX callbacks here. TX callbacks must be handled based 197 * on the TUSB DMA status interrupt. 198 * REVISIT: Use both TUSB DMA status interrupt and OMAP DMA callback 199 * interrupt for RX and TX. 200 */ 201 if (!chdat->tx) 202 musb_dma_completion(musb, chdat->epnum, chdat->tx); 203 204 /* We must terminate short tx transfers manually by setting TXPKTRDY. 205 * REVISIT: This same problem may occur with other MUSB dma as well. 206 * Easy to test with g_ether by pinging the MUSB board with ping -s54. 207 */ 208 if ((chdat->transfer_len < chdat->packet_sz) 209 || (chdat->transfer_len % chdat->packet_sz != 0)) { 210 u16 csr; 211 212 if (chdat->tx) { 213 dev_dbg(musb->controller, "terminating short tx packet\n"); 214 musb_ep_select(mbase, chdat->epnum); 215 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 216 csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY 217 | MUSB_TXCSR_P_WZC_BITS; 218 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 219 } 220 } 221 222 spin_unlock_irqrestore(&musb->lock, flags); 223} 224 225static int tusb_omap_dma_program(struct dma_channel *channel, u16 packet_sz, 226 u8 rndis_mode, dma_addr_t dma_addr, u32 len) 227{ 228 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 229 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 230 struct musb *musb = chdat->musb; 231 struct device *dev = musb->controller; 232 struct musb_hw_ep *hw_ep = chdat->hw_ep; 233 void __iomem *mbase = musb->mregs; 234 void __iomem *ep_conf = hw_ep->conf; 235 dma_addr_t fifo = hw_ep->fifo_sync; 236 struct omap_dma_channel_params dma_params; 237 u32 dma_remaining; 238 int src_burst, dst_burst; 239 u16 csr; 240 int ch; 241 s8 dmareq; 242 s8 sync_dev; 243 244 if (unlikely(dma_addr & 0x1) || (len < 32) || (len > packet_sz)) 245 return false; 246 247 /* 248 * HW issue #10: Async dma will eventually corrupt the XFR_SIZE 249 * register which will cause missed DMA interrupt. We could try to 250 * use a timer for the callback, but it is unsafe as the XFR_SIZE 251 * register is corrupt, and we won't know if the DMA worked. 252 */ 253 if (dma_addr & 0x2) 254 return false; 255 256 /* 257 * Because of HW issue #10, it seems like mixing sync DMA and async 258 * PIO access can confuse the DMA. Make sure XFR_SIZE is reset before 259 * using the channel for DMA. 260 */ 261 if (chdat->tx) 262 dma_remaining = musb_readl(ep_conf, TUSB_EP_TX_OFFSET); 263 else 264 dma_remaining = musb_readl(ep_conf, TUSB_EP_RX_OFFSET); 265 266 dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining); 267 if (dma_remaining) { 268 dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n", 269 chdat->tx ? "tx" : "rx", chdat->ch, 270 dma_remaining); 271 return false; 272 } 273 274 chdat->transfer_len = len & ~0x1f; 275 276 if (len < packet_sz) 277 chdat->transfer_packet_sz = chdat->transfer_len; 278 else 279 chdat->transfer_packet_sz = packet_sz; 280 281 if (tusb_dma->multichannel) { 282 ch = chdat->ch; 283 dmareq = chdat->dmareq; 284 sync_dev = chdat->sync_dev; 285 } else { 286 if (tusb_omap_use_shared_dmareq(chdat) != 0) { 287 dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum); 288 return false; 289 } 290 if (tusb_dma->ch < 0) { 291 /* REVISIT: This should get blocked earlier, happens 292 * with MSC ErrorRecoveryTest 293 */ 294 WARN_ON(1); 295 return false; 296 } 297 298 ch = tusb_dma->ch; 299 dmareq = tusb_dma->dmareq; 300 sync_dev = tusb_dma->sync_dev; 301 omap_set_dma_callback(ch, tusb_omap_dma_cb, channel); 302 } 303 304 chdat->packet_sz = packet_sz; 305 chdat->len = len; 306 channel->actual_len = 0; 307 chdat->dma_addr = dma_addr; 308 channel->status = MUSB_DMA_STATUS_BUSY; 309 310 /* Since we're recycling dma areas, we need to clean or invalidate */ 311 if (chdat->tx) 312 dma_map_single(dev, phys_to_virt(dma_addr), len, 313 DMA_TO_DEVICE); 314 else 315 dma_map_single(dev, phys_to_virt(dma_addr), len, 316 DMA_FROM_DEVICE); 317 318 /* Use 16-bit transfer if dma_addr is not 32-bit aligned */ 319 if ((dma_addr & 0x3) == 0) { 320 dma_params.data_type = OMAP_DMA_DATA_TYPE_S32; 321 dma_params.elem_count = 8; /* Elements in frame */ 322 } else { 323 dma_params.data_type = OMAP_DMA_DATA_TYPE_S16; 324 dma_params.elem_count = 16; /* Elements in frame */ 325 fifo = hw_ep->fifo_async; 326 } 327 328 dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */ 329 330 dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n", 331 chdat->epnum, chdat->tx ? "tx" : "rx", 332 ch, dma_addr, chdat->transfer_len, len, 333 chdat->transfer_packet_sz, packet_sz); 334 335 /* 336 * Prepare omap DMA for transfer 337 */ 338 if (chdat->tx) { 339 dma_params.src_amode = OMAP_DMA_AMODE_POST_INC; 340 dma_params.src_start = (unsigned long)dma_addr; 341 dma_params.src_ei = 0; 342 dma_params.src_fi = 0; 343 344 dma_params.dst_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 345 dma_params.dst_start = (unsigned long)fifo; 346 dma_params.dst_ei = 1; 347 dma_params.dst_fi = -31; /* Loop 32 byte window */ 348 349 dma_params.trigger = sync_dev; 350 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 351 dma_params.src_or_dst_synch = 0; /* Dest sync */ 352 353 src_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 read */ 354 dst_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 write */ 355 } else { 356 dma_params.src_amode = OMAP_DMA_AMODE_DOUBLE_IDX; 357 dma_params.src_start = (unsigned long)fifo; 358 dma_params.src_ei = 1; 359 dma_params.src_fi = -31; /* Loop 32 byte window */ 360 361 dma_params.dst_amode = OMAP_DMA_AMODE_POST_INC; 362 dma_params.dst_start = (unsigned long)dma_addr; 363 dma_params.dst_ei = 0; 364 dma_params.dst_fi = 0; 365 366 dma_params.trigger = sync_dev; 367 dma_params.sync_mode = OMAP_DMA_SYNC_FRAME; 368 dma_params.src_or_dst_synch = 1; /* Source sync */ 369 370 src_burst = OMAP_DMA_DATA_BURST_8; /* 8x32 read */ 371 dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */ 372 } 373 374 dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n", 375 chdat->epnum, chdat->tx ? "tx" : "rx", 376 (dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16, 377 ((dma_addr & 0x3) == 0) ? "sync" : "async", 378 dma_params.src_start, dma_params.dst_start); 379 380 omap_set_dma_params(ch, &dma_params); 381 omap_set_dma_src_burst_mode(ch, src_burst); 382 omap_set_dma_dest_burst_mode(ch, dst_burst); 383 omap_set_dma_write_mode(ch, OMAP_DMA_WRITE_LAST_NON_POSTED); 384 385 /* 386 * Prepare MUSB for DMA transfer 387 */ 388 if (chdat->tx) { 389 musb_ep_select(mbase, chdat->epnum); 390 csr = musb_readw(hw_ep->regs, MUSB_TXCSR); 391 csr |= (MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB 392 | MUSB_TXCSR_DMAMODE | MUSB_TXCSR_MODE); 393 csr &= ~MUSB_TXCSR_P_UNDERRUN; 394 musb_writew(hw_ep->regs, MUSB_TXCSR, csr); 395 } else { 396 musb_ep_select(mbase, chdat->epnum); 397 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); 398 csr |= MUSB_RXCSR_DMAENAB; 399 csr &= ~(MUSB_RXCSR_AUTOCLEAR | MUSB_RXCSR_DMAMODE); 400 musb_writew(hw_ep->regs, MUSB_RXCSR, 401 csr | MUSB_RXCSR_P_WZC_BITS); 402 } 403 404 /* 405 * Start DMA transfer 406 */ 407 omap_start_dma(ch); 408 409 if (chdat->tx) { 410 /* Send transfer_packet_sz packets at a time */ 411 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 412 chdat->transfer_packet_sz); 413 414 musb_writel(ep_conf, TUSB_EP_TX_OFFSET, 415 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 416 } else { 417 /* Receive transfer_packet_sz packets at a time */ 418 musb_writel(ep_conf, TUSB_EP_MAX_PACKET_SIZE_OFFSET, 419 chdat->transfer_packet_sz << 16); 420 421 musb_writel(ep_conf, TUSB_EP_RX_OFFSET, 422 TUSB_EP_CONFIG_XFR_SIZE(chdat->transfer_len)); 423 } 424 425 return true; 426} 427 428static int tusb_omap_dma_abort(struct dma_channel *channel) 429{ 430 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 431 struct tusb_omap_dma *tusb_dma = chdat->tusb_dma; 432 433 if (!tusb_dma->multichannel) { 434 if (tusb_dma->ch >= 0) { 435 omap_stop_dma(tusb_dma->ch); 436 omap_free_dma(tusb_dma->ch); 437 tusb_dma->ch = -1; 438 } 439 440 tusb_dma->dmareq = -1; 441 tusb_dma->sync_dev = -1; 442 } 443 444 channel->status = MUSB_DMA_STATUS_FREE; 445 446 return 0; 447} 448 449static inline int tusb_omap_dma_allocate_dmareq(struct tusb_omap_dma_ch *chdat) 450{ 451 u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 452 int i, dmareq_nr = -1; 453 454 const int sync_dev[6] = { 455 OMAP24XX_DMA_EXT_DMAREQ0, 456 OMAP24XX_DMA_EXT_DMAREQ1, 457 OMAP242X_DMA_EXT_DMAREQ2, 458 OMAP242X_DMA_EXT_DMAREQ3, 459 OMAP242X_DMA_EXT_DMAREQ4, 460 OMAP242X_DMA_EXT_DMAREQ5, 461 }; 462 463 for (i = 0; i < MAX_DMAREQ; i++) { 464 int cur = (reg & (0xf << (i * 5))) >> (i * 5); 465 if (cur == 0) { 466 dmareq_nr = i; 467 break; 468 } 469 } 470 471 if (dmareq_nr == -1) 472 return -EAGAIN; 473 474 reg |= (chdat->epnum << (dmareq_nr * 5)); 475 if (chdat->tx) 476 reg |= ((1 << 4) << (dmareq_nr * 5)); 477 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 478 479 chdat->dmareq = dmareq_nr; 480 chdat->sync_dev = sync_dev[chdat->dmareq]; 481 482 return 0; 483} 484 485static inline void tusb_omap_dma_free_dmareq(struct tusb_omap_dma_ch *chdat) 486{ 487 u32 reg; 488 489 if (!chdat || chdat->dmareq < 0) 490 return; 491 492 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP); 493 reg &= ~(0x1f << (chdat->dmareq * 5)); 494 musb_writel(chdat->tbase, TUSB_DMA_EP_MAP, reg); 495 496 chdat->dmareq = -1; 497 chdat->sync_dev = -1; 498} 499 500static struct dma_channel *dma_channel_pool[MAX_DMAREQ]; 501 502static struct dma_channel * 503tusb_omap_dma_allocate(struct dma_controller *c, 504 struct musb_hw_ep *hw_ep, 505 u8 tx) 506{ 507 int ret, i; 508 const char *dev_name; 509 struct tusb_omap_dma *tusb_dma; 510 struct musb *musb; 511 void __iomem *tbase; 512 struct dma_channel *channel = NULL; 513 struct tusb_omap_dma_ch *chdat = NULL; 514 u32 reg; 515 516 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 517 musb = tusb_dma->musb; 518 tbase = musb->ctrl_base; 519 520 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 521 if (tx) 522 reg &= ~(1 << hw_ep->epnum); 523 else 524 reg &= ~(1 << (hw_ep->epnum + 15)); 525 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 526 527 /* REVISIT: Why does dmareq5 not work? */ 528 if (hw_ep->epnum == 0) { 529 dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx"); 530 return NULL; 531 } 532 533 for (i = 0; i < MAX_DMAREQ; i++) { 534 struct dma_channel *ch = dma_channel_pool[i]; 535 if (ch->status == MUSB_DMA_STATUS_UNKNOWN) { 536 ch->status = MUSB_DMA_STATUS_FREE; 537 channel = ch; 538 chdat = ch->private_data; 539 break; 540 } 541 } 542 543 if (!channel) 544 return NULL; 545 546 if (tx) { 547 chdat->tx = 1; 548 dev_name = "TUSB transmit"; 549 } else { 550 chdat->tx = 0; 551 dev_name = "TUSB receive"; 552 } 553 554 chdat->musb = tusb_dma->musb; 555 chdat->tbase = tusb_dma->tbase; 556 chdat->hw_ep = hw_ep; 557 chdat->epnum = hw_ep->epnum; 558 chdat->dmareq = -1; 559 chdat->completed_len = 0; 560 chdat->tusb_dma = tusb_dma; 561 562 channel->max_len = 0x7fffffff; 563 channel->desired_mode = 0; 564 channel->actual_len = 0; 565 566 if (tusb_dma->multichannel) { 567 ret = tusb_omap_dma_allocate_dmareq(chdat); 568 if (ret != 0) 569 goto free_dmareq; 570 571 ret = omap_request_dma(chdat->sync_dev, dev_name, 572 tusb_omap_dma_cb, channel, &chdat->ch); 573 if (ret != 0) 574 goto free_dmareq; 575 } else if (tusb_dma->ch == -1) { 576 tusb_dma->dmareq = 0; 577 tusb_dma->sync_dev = OMAP24XX_DMA_EXT_DMAREQ0; 578 579 /* Callback data gets set later in the shared dmareq case */ 580 ret = omap_request_dma(tusb_dma->sync_dev, "TUSB shared", 581 tusb_omap_dma_cb, NULL, &tusb_dma->ch); 582 if (ret != 0) 583 goto free_dmareq; 584 585 chdat->dmareq = -1; 586 chdat->ch = -1; 587 } 588 589 dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n", 590 chdat->epnum, 591 chdat->tx ? "tx" : "rx", 592 chdat->ch >= 0 ? "dedicated" : "shared", 593 chdat->ch >= 0 ? chdat->ch : tusb_dma->ch, 594 chdat->dmareq >= 0 ? chdat->dmareq : tusb_dma->dmareq, 595 chdat->sync_dev >= 0 ? chdat->sync_dev : tusb_dma->sync_dev); 596 597 return channel; 598 599free_dmareq: 600 tusb_omap_dma_free_dmareq(chdat); 601 602 dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum); 603 channel->status = MUSB_DMA_STATUS_UNKNOWN; 604 605 return NULL; 606} 607 608static void tusb_omap_dma_release(struct dma_channel *channel) 609{ 610 struct tusb_omap_dma_ch *chdat = to_chdat(channel); 611 struct musb *musb = chdat->musb; 612 void __iomem *tbase = musb->ctrl_base; 613 u32 reg; 614 615 dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch); 616 617 reg = musb_readl(tbase, TUSB_DMA_INT_MASK); 618 if (chdat->tx) 619 reg |= (1 << chdat->epnum); 620 else 621 reg |= (1 << (chdat->epnum + 15)); 622 musb_writel(tbase, TUSB_DMA_INT_MASK, reg); 623 624 reg = musb_readl(tbase, TUSB_DMA_INT_CLEAR); 625 if (chdat->tx) 626 reg |= (1 << chdat->epnum); 627 else 628 reg |= (1 << (chdat->epnum + 15)); 629 musb_writel(tbase, TUSB_DMA_INT_CLEAR, reg); 630 631 channel->status = MUSB_DMA_STATUS_UNKNOWN; 632 633 if (chdat->ch >= 0) { 634 omap_stop_dma(chdat->ch); 635 omap_free_dma(chdat->ch); 636 chdat->ch = -1; 637 } 638 639 if (chdat->dmareq >= 0) 640 tusb_omap_dma_free_dmareq(chdat); 641 642 channel = NULL; 643} 644 645void dma_controller_destroy(struct dma_controller *c) 646{ 647 struct tusb_omap_dma *tusb_dma; 648 int i; 649 650 tusb_dma = container_of(c, struct tusb_omap_dma, controller); 651 for (i = 0; i < MAX_DMAREQ; i++) { 652 struct dma_channel *ch = dma_channel_pool[i]; 653 if (ch) { 654 kfree(ch->private_data); 655 kfree(ch); 656 } 657 } 658 659 if (tusb_dma && !tusb_dma->multichannel && tusb_dma->ch >= 0) 660 omap_free_dma(tusb_dma->ch); 661 662 kfree(tusb_dma); 663} 664 665struct dma_controller *__init 666dma_controller_create(struct musb *musb, void __iomem *base) 667{ 668 void __iomem *tbase = musb->ctrl_base; 669 struct tusb_omap_dma *tusb_dma; 670 int i; 671 672 /* REVISIT: Get dmareq lines used from board-*.c */ 673 674 musb_writel(musb->ctrl_base, TUSB_DMA_INT_MASK, 0x7fffffff); 675 musb_writel(musb->ctrl_base, TUSB_DMA_EP_MAP, 0); 676 677 musb_writel(tbase, TUSB_DMA_REQ_CONF, 678 TUSB_DMA_REQ_CONF_BURST_SIZE(2) 679 | TUSB_DMA_REQ_CONF_DMA_REQ_EN(0x3f) 680 | TUSB_DMA_REQ_CONF_DMA_REQ_ASSER(2)); 681 682 tusb_dma = kzalloc(sizeof(struct tusb_omap_dma), GFP_KERNEL); 683 if (!tusb_dma) 684 goto out; 685 686 tusb_dma->musb = musb; 687 tusb_dma->tbase = musb->ctrl_base; 688 689 tusb_dma->ch = -1; 690 tusb_dma->dmareq = -1; 691 tusb_dma->sync_dev = -1; 692 693 tusb_dma->controller.start = tusb_omap_dma_start; 694 tusb_dma->controller.stop = tusb_omap_dma_stop; 695 tusb_dma->controller.channel_alloc = tusb_omap_dma_allocate; 696 tusb_dma->controller.channel_release = tusb_omap_dma_release; 697 tusb_dma->controller.channel_program = tusb_omap_dma_program; 698 tusb_dma->controller.channel_abort = tusb_omap_dma_abort; 699 700 if (tusb_get_revision(musb) >= TUSB_REV_30) 701 tusb_dma->multichannel = 1; 702 703 for (i = 0; i < MAX_DMAREQ; i++) { 704 struct dma_channel *ch; 705 struct tusb_omap_dma_ch *chdat; 706 707 ch = kzalloc(sizeof(struct dma_channel), GFP_KERNEL); 708 if (!ch) 709 goto cleanup; 710 711 dma_channel_pool[i] = ch; 712 713 chdat = kzalloc(sizeof(struct tusb_omap_dma_ch), GFP_KERNEL); 714 if (!chdat) 715 goto cleanup; 716 717 ch->status = MUSB_DMA_STATUS_UNKNOWN; 718 ch->private_data = chdat; 719 } 720 721 return &tusb_dma->controller; 722 723cleanup: 724 dma_controller_destroy(&tusb_dma->controller); 725out: 726 return NULL; 727} 728