1/* 2 * linux/drivers/video/omap2/dss/dss.h 3 * 4 * Copyright (C) 2009 Nokia Corporation 5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> 6 * 7 * Some code and ideas taken from drivers/video/omap/ driver 8 * by Imre Deak. 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License version 2 as published by 12 * the Free Software Foundation. 13 * 14 * This program is distributed in the hope that it will be useful, but WITHOUT 15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 17 * more details. 18 * 19 * You should have received a copy of the GNU General Public License along with 20 * this program. If not, see <http://www.gnu.org/licenses/>. 21 */ 22 23#ifndef __OMAP2_DSS_H 24#define __OMAP2_DSS_H 25 26#ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT 27#define DEBUG 28#endif 29 30#ifdef DEBUG 31extern bool dss_debug; 32#ifdef DSS_SUBSYS_NAME 33#define DSSDBG(format, ...) \ 34 if (dss_debug) \ 35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \ 36 ## __VA_ARGS__) 37#else 38#define DSSDBG(format, ...) \ 39 if (dss_debug) \ 40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__) 41#endif 42 43#ifdef DSS_SUBSYS_NAME 44#define DSSDBGF(format, ...) \ 45 if (dss_debug) \ 46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \ 47 ": %s(" format ")\n", \ 48 __func__, \ 49 ## __VA_ARGS__) 50#else 51#define DSSDBGF(format, ...) \ 52 if (dss_debug) \ 53 printk(KERN_DEBUG "omapdss: " \ 54 ": %s(" format ")\n", \ 55 __func__, \ 56 ## __VA_ARGS__) 57#endif 58 59#else /* DEBUG */ 60#define DSSDBG(format, ...) 61#define DSSDBGF(format, ...) 62#endif 63 64 65#ifdef DSS_SUBSYS_NAME 66#define DSSERR(format, ...) \ 67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \ 68 ## __VA_ARGS__) 69#else 70#define DSSERR(format, ...) \ 71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__) 72#endif 73 74#ifdef DSS_SUBSYS_NAME 75#define DSSINFO(format, ...) \ 76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \ 77 ## __VA_ARGS__) 78#else 79#define DSSINFO(format, ...) \ 80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__) 81#endif 82 83#ifdef DSS_SUBSYS_NAME 84#define DSSWARN(format, ...) \ 85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \ 86 ## __VA_ARGS__) 87#else 88#define DSSWARN(format, ...) \ 89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__) 90#endif 91 92/* OMAP TRM gives bitfields as start:end, where start is the higher bit 93 number. For example 7:0 */ 94#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) 95#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) 96#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end)) 97#define FLD_MOD(orig, val, start, end) \ 98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 99 100enum dss_io_pad_mode { 101 DSS_IO_PAD_MODE_RESET, 102 DSS_IO_PAD_MODE_RFBI, 103 DSS_IO_PAD_MODE_BYPASS, 104}; 105 106enum dss_hdmi_venc_clk_source_select { 107 DSS_VENC_TV_CLK = 0, 108 DSS_HDMI_M_PCLK = 1, 109}; 110 111enum dss_dsi_content_type { 112 DSS_DSI_CONTENT_DCS, 113 DSS_DSI_CONTENT_GENERIC, 114}; 115 116struct dss_clock_info { 117 /* rates that we get with dividers below */ 118 unsigned long fck; 119 120 /* dividers */ 121 u16 fck_div; 122}; 123 124struct dispc_clock_info { 125 /* rates that we get with dividers below */ 126 unsigned long lck; 127 unsigned long pck; 128 129 /* dividers */ 130 u16 lck_div; 131 u16 pck_div; 132}; 133 134struct dsi_clock_info { 135 /* rates that we get with dividers below */ 136 unsigned long fint; 137 unsigned long clkin4ddr; 138 unsigned long clkin; 139 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK 140 * OMAP4: PLLx_CLK1 */ 141 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK 142 * OMAP4: PLLx_CLK2 */ 143 unsigned long lp_clk; 144 145 /* dividers */ 146 u16 regn; 147 u16 regm; 148 u16 regm_dispc; /* OMAP3: REGM3 149 * OMAP4: REGM4 */ 150 u16 regm_dsi; /* OMAP3: REGM4 151 * OMAP4: REGM5 */ 152 u16 lp_clk_div; 153 154 u8 highfreq; 155 bool use_sys_clk; 156}; 157 158struct seq_file; 159struct platform_device; 160 161/* core */ 162struct bus_type *dss_get_bus(void); 163struct regulator *dss_get_vdds_dsi(void); 164struct regulator *dss_get_vdds_sdi(void); 165 166/* apply */ 167void dss_apply_init(void); 168int dss_mgr_wait_for_go(struct omap_overlay_manager *mgr); 169int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl); 170void dss_mgr_start_update(struct omap_overlay_manager *mgr); 171int omap_dss_mgr_apply(struct omap_overlay_manager *mgr); 172 173int dss_mgr_enable(struct omap_overlay_manager *mgr); 174void dss_mgr_disable(struct omap_overlay_manager *mgr); 175int dss_mgr_set_info(struct omap_overlay_manager *mgr, 176 struct omap_overlay_manager_info *info); 177void dss_mgr_get_info(struct omap_overlay_manager *mgr, 178 struct omap_overlay_manager_info *info); 179int dss_mgr_set_device(struct omap_overlay_manager *mgr, 180 struct omap_dss_device *dssdev); 181int dss_mgr_unset_device(struct omap_overlay_manager *mgr); 182 183bool dss_ovl_is_enabled(struct omap_overlay *ovl); 184int dss_ovl_enable(struct omap_overlay *ovl); 185int dss_ovl_disable(struct omap_overlay *ovl); 186int dss_ovl_set_info(struct omap_overlay *ovl, 187 struct omap_overlay_info *info); 188void dss_ovl_get_info(struct omap_overlay *ovl, 189 struct omap_overlay_info *info); 190int dss_ovl_set_manager(struct omap_overlay *ovl, 191 struct omap_overlay_manager *mgr); 192int dss_ovl_unset_manager(struct omap_overlay *ovl); 193 194/* display */ 195int dss_suspend_all_devices(void); 196int dss_resume_all_devices(void); 197void dss_disable_all_devices(void); 198 199void dss_init_device(struct platform_device *pdev, 200 struct omap_dss_device *dssdev); 201void dss_uninit_device(struct platform_device *pdev, 202 struct omap_dss_device *dssdev); 203bool dss_use_replication(struct omap_dss_device *dssdev, 204 enum omap_color_mode mode); 205 206/* manager */ 207int dss_init_overlay_managers(struct platform_device *pdev); 208void dss_uninit_overlay_managers(struct platform_device *pdev); 209int dss_mgr_simple_check(struct omap_overlay_manager *mgr, 210 const struct omap_overlay_manager_info *info); 211int dss_mgr_check(struct omap_overlay_manager *mgr, 212 struct omap_dss_device *dssdev, 213 struct omap_overlay_manager_info *info, 214 struct omap_overlay_info **overlay_infos); 215 216/* overlay */ 217void dss_init_overlays(struct platform_device *pdev); 218void dss_uninit_overlays(struct platform_device *pdev); 219void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr); 220void dss_recheck_connections(struct omap_dss_device *dssdev, bool force); 221int dss_ovl_simple_check(struct omap_overlay *ovl, 222 const struct omap_overlay_info *info); 223int dss_ovl_check(struct omap_overlay *ovl, 224 struct omap_overlay_info *info, struct omap_dss_device *dssdev); 225 226/* DSS */ 227int dss_init_platform_driver(void); 228void dss_uninit_platform_driver(void); 229 230int dss_runtime_get(void); 231void dss_runtime_put(void); 232 233void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); 234enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); 235const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src); 236void dss_dump_clocks(struct seq_file *s); 237 238void dss_dump_regs(struct seq_file *s); 239#if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) 240void dss_debug_dump_clocks(struct seq_file *s); 241#endif 242 243void dss_sdi_init(u8 datapairs); 244int dss_sdi_enable(void); 245void dss_sdi_disable(void); 246 247void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src); 248void dss_select_dsi_clk_source(int dsi_module, 249 enum omap_dss_clk_source clk_src); 250void dss_select_lcd_clk_source(enum omap_channel channel, 251 enum omap_dss_clk_source clk_src); 252enum omap_dss_clk_source dss_get_dispc_clk_source(void); 253enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module); 254enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 255 256void dss_set_venc_output(enum omap_dss_venc_type type); 257void dss_set_dac_pwrdn_bgz(bool enable); 258 259unsigned long dss_get_dpll4_rate(void); 260int dss_calc_clock_rates(struct dss_clock_info *cinfo); 261int dss_set_clock_div(struct dss_clock_info *cinfo); 262int dss_get_clock_div(struct dss_clock_info *cinfo); 263int dss_calc_clock_div(bool is_tft, unsigned long req_pck, 264 struct dss_clock_info *dss_cinfo, 265 struct dispc_clock_info *dispc_cinfo); 266 267/* SDI */ 268#ifdef CONFIG_OMAP2_DSS_SDI 269int sdi_init(void); 270void sdi_exit(void); 271int sdi_init_display(struct omap_dss_device *display); 272#else 273static inline int sdi_init(void) 274{ 275 return 0; 276} 277static inline void sdi_exit(void) 278{ 279} 280#endif 281 282/* DSI */ 283#ifdef CONFIG_OMAP2_DSS_DSI 284 285struct dentry; 286struct file_operations; 287 288int dsi_init_platform_driver(void); 289void dsi_uninit_platform_driver(void); 290 291int dsi_runtime_get(struct platform_device *dsidev); 292void dsi_runtime_put(struct platform_device *dsidev); 293 294void dsi_dump_clocks(struct seq_file *s); 295void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir, 296 const struct file_operations *debug_fops); 297void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir, 298 const struct file_operations *debug_fops); 299 300int dsi_init_display(struct omap_dss_device *display); 301void dsi_irq_handler(void); 302u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt); 303 304unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev); 305int dsi_pll_set_clock_div(struct platform_device *dsidev, 306 struct dsi_clock_info *cinfo); 307int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft, 308 unsigned long req_pck, struct dsi_clock_info *cinfo, 309 struct dispc_clock_info *dispc_cinfo); 310int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, 311 bool enable_hsdiv); 312void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes); 313void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev); 314void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev); 315struct platform_device *dsi_get_dsidev_from_id(int module); 316#else 317static inline int dsi_init_platform_driver(void) 318{ 319 return 0; 320} 321static inline void dsi_uninit_platform_driver(void) 322{ 323} 324static inline int dsi_runtime_get(struct platform_device *dsidev) 325{ 326 return 0; 327} 328static inline void dsi_runtime_put(struct platform_device *dsidev) 329{ 330} 331static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 332{ 333 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__); 334 return 0; 335} 336static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) 337{ 338 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__); 339 return 0; 340} 341static inline int dsi_pll_set_clock_div(struct platform_device *dsidev, 342 struct dsi_clock_info *cinfo) 343{ 344 WARN("%s: DSI not compiled in\n", __func__); 345 return -ENODEV; 346} 347static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, 348 bool is_tft, unsigned long req_pck, 349 struct dsi_clock_info *dsi_cinfo, 350 struct dispc_clock_info *dispc_cinfo) 351{ 352 WARN("%s: DSI not compiled in\n", __func__); 353 return -ENODEV; 354} 355static inline int dsi_pll_init(struct platform_device *dsidev, 356 bool enable_hsclk, bool enable_hsdiv) 357{ 358 WARN("%s: DSI not compiled in\n", __func__); 359 return -ENODEV; 360} 361static inline void dsi_pll_uninit(struct platform_device *dsidev, 362 bool disconnect_lanes) 363{ 364} 365static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) 366{ 367} 368static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) 369{ 370} 371static inline struct platform_device *dsi_get_dsidev_from_id(int module) 372{ 373 WARN("%s: DSI not compiled in, returning platform device as NULL\n", 374 __func__); 375 return NULL; 376} 377#endif 378 379/* DPI */ 380#ifdef CONFIG_OMAP2_DSS_DPI 381int dpi_init(void); 382void dpi_exit(void); 383int dpi_init_display(struct omap_dss_device *dssdev); 384#else 385static inline int dpi_init(void) 386{ 387 return 0; 388} 389static inline void dpi_exit(void) 390{ 391} 392#endif 393 394/* DISPC */ 395int dispc_init_platform_driver(void); 396void dispc_uninit_platform_driver(void); 397void dispc_dump_clocks(struct seq_file *s); 398void dispc_dump_irqs(struct seq_file *s); 399void dispc_dump_regs(struct seq_file *s); 400void dispc_irq_handler(void); 401void dispc_fake_vsync_irq(void); 402 403int dispc_runtime_get(void); 404void dispc_runtime_put(void); 405 406void dispc_enable_sidle(void); 407void dispc_disable_sidle(void); 408 409void dispc_lcd_enable_signal_polarity(bool act_high); 410void dispc_lcd_enable_signal(bool enable); 411void dispc_pck_free_enable(bool enable); 412void dispc_set_digit_size(u16 width, u16 height); 413void dispc_enable_fifomerge(bool enable); 414void dispc_enable_gamma_table(bool enable); 415void dispc_set_loadmode(enum omap_dss_load_mode mode); 416 417bool dispc_lcd_timings_ok(struct omap_video_timings *timings); 418unsigned long dispc_fclk_rate(void); 419void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, 420 struct dispc_clock_info *cinfo); 421int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, 422 struct dispc_clock_info *cinfo); 423 424 425void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high); 426void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, 427 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, 428 bool manual_update); 429int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi, 430 bool ilace, bool replication); 431int dispc_ovl_enable(enum omap_plane plane, bool enable); 432void dispc_ovl_set_channel_out(enum omap_plane plane, 433 enum omap_channel channel); 434 435void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable); 436void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height); 437u32 dispc_mgr_get_vsync_irq(enum omap_channel channel); 438u32 dispc_mgr_get_framedone_irq(enum omap_channel channel); 439bool dispc_mgr_go_busy(enum omap_channel channel); 440void dispc_mgr_go(enum omap_channel channel); 441bool dispc_mgr_is_enabled(enum omap_channel channel); 442void dispc_mgr_enable(enum omap_channel channel, bool enable); 443bool dispc_mgr_is_channel_enabled(enum omap_channel channel); 444void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode); 445void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable); 446void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines); 447void dispc_mgr_set_lcd_display_type(enum omap_channel channel, 448 enum omap_lcd_display_type type); 449void dispc_mgr_set_lcd_timings(enum omap_channel channel, 450 struct omap_video_timings *timings); 451void dispc_mgr_set_pol_freq(enum omap_channel channel, 452 enum omap_panel_config config, u8 acbi, u8 acb); 453unsigned long dispc_mgr_lclk_rate(enum omap_channel channel); 454unsigned long dispc_mgr_pclk_rate(enum omap_channel channel); 455int dispc_mgr_set_clock_div(enum omap_channel channel, 456 struct dispc_clock_info *cinfo); 457int dispc_mgr_get_clock_div(enum omap_channel channel, 458 struct dispc_clock_info *cinfo); 459void dispc_mgr_setup(enum omap_channel channel, 460 struct omap_overlay_manager_info *info); 461 462/* VENC */ 463#ifdef CONFIG_OMAP2_DSS_VENC 464int venc_init_platform_driver(void); 465void venc_uninit_platform_driver(void); 466void venc_dump_regs(struct seq_file *s); 467int venc_init_display(struct omap_dss_device *display); 468unsigned long venc_get_pixel_clock(void); 469#else 470static inline int venc_init_platform_driver(void) 471{ 472 return 0; 473} 474static inline void venc_uninit_platform_driver(void) 475{ 476} 477static inline unsigned long venc_get_pixel_clock(void) 478{ 479 WARN("%s: VENC not compiled in, returning pclk as 0\n", __func__); 480 return 0; 481} 482#endif 483 484/* HDMI */ 485#ifdef CONFIG_OMAP4_DSS_HDMI 486int hdmi_init_platform_driver(void); 487void hdmi_uninit_platform_driver(void); 488int hdmi_init_display(struct omap_dss_device *dssdev); 489unsigned long hdmi_get_pixel_clock(void); 490void hdmi_dump_regs(struct seq_file *s); 491#else 492static inline int hdmi_init_display(struct omap_dss_device *dssdev) 493{ 494 return 0; 495} 496static inline int hdmi_init_platform_driver(void) 497{ 498 return 0; 499} 500static inline void hdmi_uninit_platform_driver(void) 501{ 502} 503static inline unsigned long hdmi_get_pixel_clock(void) 504{ 505 WARN("%s: HDMI not compiled in, returning pclk as 0\n", __func__); 506 return 0; 507} 508#endif 509int omapdss_hdmi_display_enable(struct omap_dss_device *dssdev); 510void omapdss_hdmi_display_disable(struct omap_dss_device *dssdev); 511void omapdss_hdmi_display_set_timing(struct omap_dss_device *dssdev); 512int omapdss_hdmi_display_check_timing(struct omap_dss_device *dssdev, 513 struct omap_video_timings *timings); 514int omapdss_hdmi_read_edid(u8 *buf, int len); 515bool omapdss_hdmi_detect(void); 516int hdmi_panel_init(void); 517void hdmi_panel_exit(void); 518 519/* RFBI */ 520#ifdef CONFIG_OMAP2_DSS_RFBI 521int rfbi_init_platform_driver(void); 522void rfbi_uninit_platform_driver(void); 523void rfbi_dump_regs(struct seq_file *s); 524int rfbi_init_display(struct omap_dss_device *display); 525#else 526static inline int rfbi_init_platform_driver(void) 527{ 528 return 0; 529} 530static inline void rfbi_uninit_platform_driver(void) 531{ 532} 533#endif 534 535 536#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 537static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr) 538{ 539 int b; 540 for (b = 0; b < 32; ++b) { 541 if (irqstatus & (1 << b)) 542 irq_arr[b]++; 543 } 544} 545#endif 546 547#endif 548