1/* 2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> 3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> 4 * Copyright (c) 2008 Red Hat Inc. 5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA 6 * Copyright (c) 2007-2008 Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 24 * IN THE SOFTWARE. 25 */ 26 27#ifndef _DRM_MODE_H 28#define _DRM_MODE_H 29 30#include <linux/types.h> 31 32#define DRM_DISPLAY_INFO_LEN 32 33#define DRM_CONNECTOR_NAME_LEN 32 34#define DRM_DISPLAY_MODE_LEN 32 35#define DRM_PROP_NAME_LEN 32 36 37#define DRM_MODE_TYPE_BUILTIN (1<<0) 38#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) 39#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) 40#define DRM_MODE_TYPE_PREFERRED (1<<3) 41#define DRM_MODE_TYPE_DEFAULT (1<<4) 42#define DRM_MODE_TYPE_USERDEF (1<<5) 43#define DRM_MODE_TYPE_DRIVER (1<<6) 44 45/* Video mode flags */ 46/* bit compatible with the xorg definitions. */ 47#define DRM_MODE_FLAG_PHSYNC (1<<0) 48#define DRM_MODE_FLAG_NHSYNC (1<<1) 49#define DRM_MODE_FLAG_PVSYNC (1<<2) 50#define DRM_MODE_FLAG_NVSYNC (1<<3) 51#define DRM_MODE_FLAG_INTERLACE (1<<4) 52#define DRM_MODE_FLAG_DBLSCAN (1<<5) 53#define DRM_MODE_FLAG_CSYNC (1<<6) 54#define DRM_MODE_FLAG_PCSYNC (1<<7) 55#define DRM_MODE_FLAG_NCSYNC (1<<8) 56#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ 57#define DRM_MODE_FLAG_BCAST (1<<10) 58#define DRM_MODE_FLAG_PIXMUX (1<<11) 59#define DRM_MODE_FLAG_DBLCLK (1<<12) 60#define DRM_MODE_FLAG_CLKDIV2 (1<<13) 61 62/* DPMS flags */ 63/* bit compatible with the xorg definitions. */ 64#define DRM_MODE_DPMS_ON 0 65#define DRM_MODE_DPMS_STANDBY 1 66#define DRM_MODE_DPMS_SUSPEND 2 67#define DRM_MODE_DPMS_OFF 3 68 69/* Scaling mode options */ 70#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or 71 software can still scale) */ 72#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ 73#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ 74#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ 75 76/* Dithering mode options */ 77#define DRM_MODE_DITHERING_OFF 0 78#define DRM_MODE_DITHERING_ON 1 79#define DRM_MODE_DITHERING_AUTO 2 80 81/* Dirty info options */ 82#define DRM_MODE_DIRTY_OFF 0 83#define DRM_MODE_DIRTY_ON 1 84#define DRM_MODE_DIRTY_ANNOTATE 2 85 86struct drm_mode_modeinfo { 87 __u32 clock; 88 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; 89 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; 90 91 __u32 vrefresh; 92 93 __u32 flags; 94 __u32 type; 95 char name[DRM_DISPLAY_MODE_LEN]; 96}; 97 98struct drm_mode_card_res { 99 __u64 fb_id_ptr; 100 __u64 crtc_id_ptr; 101 __u64 connector_id_ptr; 102 __u64 encoder_id_ptr; 103 __u32 count_fbs; 104 __u32 count_crtcs; 105 __u32 count_connectors; 106 __u32 count_encoders; 107 __u32 min_width, max_width; 108 __u32 min_height, max_height; 109}; 110 111struct drm_mode_crtc { 112 __u64 set_connectors_ptr; 113 __u32 count_connectors; 114 115 __u32 crtc_id; /**< Id */ 116 __u32 fb_id; /**< Id of framebuffer */ 117 118 __u32 x, y; /**< Position on the frameuffer */ 119 120 __u32 gamma_size; 121 __u32 mode_valid; 122 struct drm_mode_modeinfo mode; 123}; 124 125#define DRM_MODE_PRESENT_TOP_FIELD (1<<0) 126#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) 127 128/* Planes blend with or override other bits on the CRTC */ 129struct drm_mode_set_plane { 130 __u32 plane_id; 131 __u32 crtc_id; 132 __u32 fb_id; /* fb object contains surface format type */ 133 __u32 flags; /* see above flags */ 134 135 /* Signed dest location allows it to be partially off screen */ 136 __s32 crtc_x, crtc_y; 137 __u32 crtc_w, crtc_h; 138 139 /* Source values are 16.16 fixed point */ 140 __u32 src_x, src_y; 141 __u32 src_h, src_w; 142}; 143 144struct drm_mode_get_plane { 145 __u32 plane_id; 146 147 __u32 crtc_id; 148 __u32 fb_id; 149 150 __u32 possible_crtcs; 151 __u32 gamma_size; 152 153 __u32 count_format_types; 154 __u64 format_type_ptr; 155}; 156 157struct drm_mode_get_plane_res { 158 __u64 plane_id_ptr; 159 __u32 count_planes; 160}; 161 162#define DRM_MODE_ENCODER_NONE 0 163#define DRM_MODE_ENCODER_DAC 1 164#define DRM_MODE_ENCODER_TMDS 2 165#define DRM_MODE_ENCODER_LVDS 3 166#define DRM_MODE_ENCODER_TVDAC 4 167#define DRM_MODE_ENCODER_VIRTUAL 5 168 169struct drm_mode_get_encoder { 170 __u32 encoder_id; 171 __u32 encoder_type; 172 173 __u32 crtc_id; /**< Id of crtc */ 174 175 __u32 possible_crtcs; 176 __u32 possible_clones; 177}; 178 179/* This is for connectors with multiple signal types. */ 180/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ 181#define DRM_MODE_SUBCONNECTOR_Automatic 0 182#define DRM_MODE_SUBCONNECTOR_Unknown 0 183#define DRM_MODE_SUBCONNECTOR_DVID 3 184#define DRM_MODE_SUBCONNECTOR_DVIA 4 185#define DRM_MODE_SUBCONNECTOR_Composite 5 186#define DRM_MODE_SUBCONNECTOR_SVIDEO 6 187#define DRM_MODE_SUBCONNECTOR_Component 8 188#define DRM_MODE_SUBCONNECTOR_SCART 9 189 190#define DRM_MODE_CONNECTOR_Unknown 0 191#define DRM_MODE_CONNECTOR_VGA 1 192#define DRM_MODE_CONNECTOR_DVII 2 193#define DRM_MODE_CONNECTOR_DVID 3 194#define DRM_MODE_CONNECTOR_DVIA 4 195#define DRM_MODE_CONNECTOR_Composite 5 196#define DRM_MODE_CONNECTOR_SVIDEO 6 197#define DRM_MODE_CONNECTOR_LVDS 7 198#define DRM_MODE_CONNECTOR_Component 8 199#define DRM_MODE_CONNECTOR_9PinDIN 9 200#define DRM_MODE_CONNECTOR_DisplayPort 10 201#define DRM_MODE_CONNECTOR_HDMIA 11 202#define DRM_MODE_CONNECTOR_HDMIB 12 203#define DRM_MODE_CONNECTOR_TV 13 204#define DRM_MODE_CONNECTOR_eDP 14 205#define DRM_MODE_CONNECTOR_VIRTUAL 15 206 207struct drm_mode_get_connector { 208 209 __u64 encoders_ptr; 210 __u64 modes_ptr; 211 __u64 props_ptr; 212 __u64 prop_values_ptr; 213 214 __u32 count_modes; 215 __u32 count_props; 216 __u32 count_encoders; 217 218 __u32 encoder_id; /**< Current Encoder */ 219 __u32 connector_id; /**< Id */ 220 __u32 connector_type; 221 __u32 connector_type_id; 222 223 __u32 connection; 224 __u32 mm_width, mm_height; /**< HxW in millimeters */ 225 __u32 subpixel; 226}; 227 228#define DRM_MODE_PROP_PENDING (1<<0) 229#define DRM_MODE_PROP_RANGE (1<<1) 230#define DRM_MODE_PROP_IMMUTABLE (1<<2) 231#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ 232#define DRM_MODE_PROP_BLOB (1<<4) 233 234struct drm_mode_property_enum { 235 __u64 value; 236 char name[DRM_PROP_NAME_LEN]; 237}; 238 239struct drm_mode_get_property { 240 __u64 values_ptr; /* values and blob lengths */ 241 __u64 enum_blob_ptr; /* enum and blob id ptrs */ 242 243 __u32 prop_id; 244 __u32 flags; 245 char name[DRM_PROP_NAME_LEN]; 246 247 __u32 count_values; 248 __u32 count_enum_blobs; 249}; 250 251struct drm_mode_connector_set_property { 252 __u64 value; 253 __u32 prop_id; 254 __u32 connector_id; 255}; 256 257struct drm_mode_get_blob { 258 __u32 blob_id; 259 __u32 length; 260 __u64 data; 261}; 262 263struct drm_mode_fb_cmd { 264 __u32 fb_id; 265 __u32 width, height; 266 __u32 pitch; 267 __u32 bpp; 268 __u32 depth; 269 /* driver specific handle */ 270 __u32 handle; 271}; 272 273#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ 274 275struct drm_mode_fb_cmd2 { 276 __u32 fb_id; 277 __u32 width, height; 278 __u32 pixel_format; /* fourcc code from drm_fourcc.h */ 279 __u32 flags; /* see above flags */ 280 281 /* 282 * In case of planar formats, this ioctl allows up to 4 283 * buffer objects with offets and pitches per plane. 284 * The pitch and offset order is dictated by the fourcc, 285 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: 286 * 287 * YUV 4:2:0 image with a plane of 8 bit Y samples 288 * followed by an interleaved U/V plane containing 289 * 8 bit 2x2 subsampled colour difference samples. 290 * 291 * So it would consist of Y as offset[0] and UV as 292 * offeset[1]. Note that offset[0] will generally 293 * be 0. 294 */ 295 __u32 handles[4]; 296 __u32 pitches[4]; /* pitch for each plane */ 297 __u32 offsets[4]; /* offset of each plane */ 298}; 299 300#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 301#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 302#define DRM_MODE_FB_DIRTY_FLAGS 0x03 303 304#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 305 306/* 307 * Mark a region of a framebuffer as dirty. 308 * 309 * Some hardware does not automatically update display contents 310 * as a hardware or software draw to a framebuffer. This ioctl 311 * allows userspace to tell the kernel and the hardware what 312 * regions of the framebuffer have changed. 313 * 314 * The kernel or hardware is free to update more then just the 315 * region specified by the clip rects. The kernel or hardware 316 * may also delay and/or coalesce several calls to dirty into a 317 * single update. 318 * 319 * Userspace may annotate the updates, the annotates are a 320 * promise made by the caller that the change is either a copy 321 * of pixels or a fill of a single color in the region specified. 322 * 323 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then 324 * the number of updated regions are half of num_clips given, 325 * where the clip rects are paired in src and dst. The width and 326 * height of each one of the pairs must match. 327 * 328 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller 329 * promises that the region specified of the clip rects is filled 330 * completely with a single color as given in the color argument. 331 */ 332 333struct drm_mode_fb_dirty_cmd { 334 __u32 fb_id; 335 __u32 flags; 336 __u32 color; 337 __u32 num_clips; 338 __u64 clips_ptr; 339}; 340 341struct drm_mode_mode_cmd { 342 __u32 connector_id; 343 struct drm_mode_modeinfo mode; 344}; 345 346#define DRM_MODE_CURSOR_BO (1<<0) 347#define DRM_MODE_CURSOR_MOVE (1<<1) 348 349/* 350 * depending on the value in flags different members are used. 351 * 352 * CURSOR_BO uses 353 * crtc 354 * width 355 * height 356 * handle - if 0 turns the cursor of 357 * 358 * CURSOR_MOVE uses 359 * crtc 360 * x 361 * y 362 */ 363struct drm_mode_cursor { 364 __u32 flags; 365 __u32 crtc_id; 366 __s32 x; 367 __s32 y; 368 __u32 width; 369 __u32 height; 370 /* driver specific handle */ 371 __u32 handle; 372}; 373 374struct drm_mode_crtc_lut { 375 __u32 crtc_id; 376 __u32 gamma_size; 377 378 /* pointers to arrays */ 379 __u64 red; 380 __u64 green; 381 __u64 blue; 382}; 383 384#define DRM_MODE_PAGE_FLIP_EVENT 0x01 385#define DRM_MODE_PAGE_FLIP_FLAGS DRM_MODE_PAGE_FLIP_EVENT 386 387/* 388 * Request a page flip on the specified crtc. 389 * 390 * This ioctl will ask KMS to schedule a page flip for the specified 391 * crtc. Once any pending rendering targeting the specified fb (as of 392 * ioctl time) has completed, the crtc will be reprogrammed to display 393 * that fb after the next vertical refresh. The ioctl returns 394 * immediately, but subsequent rendering to the current fb will block 395 * in the execbuffer ioctl until the page flip happens. If a page 396 * flip is already pending as the ioctl is called, EBUSY will be 397 * returned. 398 * 399 * The ioctl supports one flag, DRM_MODE_PAGE_FLIP_EVENT, which will 400 * request that drm sends back a vblank event (see drm.h: struct 401 * drm_event_vblank) when the page flip is done. The user_data field 402 * passed in with this ioctl will be returned as the user_data field 403 * in the vblank event struct. 404 * 405 * The reserved field must be zero until we figure out something 406 * clever to use it for. 407 */ 408 409struct drm_mode_crtc_page_flip { 410 __u32 crtc_id; 411 __u32 fb_id; 412 __u32 flags; 413 __u32 reserved; 414 __u64 user_data; 415}; 416 417/* create a dumb scanout buffer */ 418struct drm_mode_create_dumb { 419 uint32_t height; 420 uint32_t width; 421 uint32_t bpp; 422 uint32_t flags; 423 /* handle, pitch, size will be returned */ 424 uint32_t handle; 425 uint32_t pitch; 426 uint64_t size; 427}; 428 429/* set up for mmap of a dumb scanout buffer */ 430struct drm_mode_map_dumb { 431 /** Handle for the object being mapped. */ 432 __u32 handle; 433 __u32 pad; 434 /** 435 * Fake offset to use for subsequent mmap call 436 * 437 * This is a fixed-size type for 32/64 compatibility. 438 */ 439 __u64 offset; 440}; 441 442struct drm_mode_destroy_dumb { 443 uint32_t handle; 444}; 445 446#endif 447