1/* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $ 2 * 3 * newport.h: Defines and register layout for NEWPORT graphics 4 * hardware. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * 8 * Ulf Carlsson - Compatibility with the IRIX structures added 9 */ 10 11#ifndef _SGI_NEWPORT_H 12#define _SGI_NEWPORT_H 13 14 15typedef volatile unsigned int npireg_t; 16 17union npfloat { 18 volatile float flt; 19 npireg_t word; 20}; 21 22typedef union npfloat npfreg_t; 23 24union np_dcb { 25 npireg_t byword; 26 struct { volatile unsigned short s0, s1; } byshort; 27 struct { volatile unsigned char b0, b1, b2, b3; } bybytes; 28}; 29 30struct newport_rexregs { 31 npireg_t drawmode1; /* GL extra mode bits */ 32 33#define DM1_PLANES 0x00000007 34#define DM1_NOPLANES 0x00000000 35#define DM1_RGBPLANES 0x00000001 36#define DM1_RGBAPLANES 0x00000002 37#define DM1_OLAYPLANES 0x00000004 38#define DM1_PUPPLANES 0x00000005 39#define DM1_CIDPLANES 0x00000006 40 41#define NPORT_DMODE1_DDMASK 0x00000018 42#define NPORT_DMODE1_DD4 0x00000000 43#define NPORT_DMODE1_DD8 0x00000008 44#define NPORT_DMODE1_DD12 0x00000010 45#define NPORT_DMODE1_DD24 0x00000018 46#define NPORT_DMODE1_DSRC 0x00000020 47#define NPORT_DMODE1_YFLIP 0x00000040 48#define NPORT_DMODE1_RWPCKD 0x00000080 49#define NPORT_DMODE1_HDMASK 0x00000300 50#define NPORT_DMODE1_HD4 0x00000000 51#define NPORT_DMODE1_HD8 0x00000100 52#define NPORT_DMODE1_HD12 0x00000200 53#define NPORT_DMODE1_HD32 0x00000300 54#define NPORT_DMODE1_RWDBL 0x00000400 55#define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */ 56#define NPORT_DMODE1_CCMASK 0x00007000 57#define NPORT_DMODE1_CCLT 0x00001000 58#define NPORT_DMODE1_CCEQ 0x00002000 59#define NPORT_DMODE1_CCGT 0x00004000 60#define NPORT_DMODE1_RGBMD 0x00008000 61#define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */ 62#define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */ 63#define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */ 64#define NPORT_DMODE1_SFMASK 0x00380000 65#define NPORT_DMODE1_SF0 0x00000000 66#define NPORT_DMODE1_SF1 0x00080000 67#define NPORT_DMODE1_SFDC 0x00100000 68#define NPORT_DMODE1_SFMDC 0x00180000 69#define NPORT_DMODE1_SFSA 0x00200000 70#define NPORT_DMODE1_SFMSA 0x00280000 71#define NPORT_DMODE1_DFMASK 0x01c00000 72#define NPORT_DMODE1_DF0 0x00000000 73#define NPORT_DMODE1_DF1 0x00400000 74#define NPORT_DMODE1_DFSC 0x00800000 75#define NPORT_DMODE1_DFMSC 0x00c00000 76#define NPORT_DMODE1_DFSA 0x01000000 77#define NPORT_DMODE1_DFMSA 0x01400000 78#define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */ 79#define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */ 80#define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */ 81#define NPORT_DMODE1_LOMASK 0xf0000000 82#define NPORT_DMODE1_LOZERO 0x00000000 83#define NPORT_DMODE1_LOAND 0x10000000 84#define NPORT_DMODE1_LOANDR 0x20000000 85#define NPORT_DMODE1_LOSRC 0x30000000 86#define NPORT_DMODE1_LOANDI 0x40000000 87#define NPORT_DMODE1_LODST 0x50000000 88#define NPORT_DMODE1_LOXOR 0x60000000 89#define NPORT_DMODE1_LOOR 0x70000000 90#define NPORT_DMODE1_LONOR 0x80000000 91#define NPORT_DMODE1_LOXNOR 0x90000000 92#define NPORT_DMODE1_LONDST 0xa0000000 93#define NPORT_DMODE1_LOORR 0xb0000000 94#define NPORT_DMODE1_LONSRC 0xc0000000 95#define NPORT_DMODE1_LOORI 0xd0000000 96#define NPORT_DMODE1_LONAND 0xe0000000 97#define NPORT_DMODE1_LOONE 0xf0000000 98 99 npireg_t drawmode0; /* REX command register */ 100 101 /* These bits define the graphics opcode being performed. */ 102#define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */ 103#define NPORT_DMODE0_NOP 0x00000000 /* No operation */ 104#define NPORT_DMODE0_RD 0x00000001 /* Read operation */ 105#define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */ 106#define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */ 107 108 /* The following decide what addressing mode(s) are to be used */ 109#define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */ 110#define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */ 111#define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */ 112#define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */ 113#define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */ 114#define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */ 115#define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */ 116#define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */ 117 118 /* And now some misc. operation control bits. */ 119#define NPORT_DMODE0_DOSETUP 0x00000020 120#define NPORT_DMODE0_CHOST 0x00000040 121#define NPORT_DMODE0_AHOST 0x00000080 122#define NPORT_DMODE0_STOPX 0x00000100 123#define NPORT_DMODE0_STOPY 0x00000200 124#define NPORT_DMODE0_SK1ST 0x00000400 125#define NPORT_DMODE0_SKLST 0x00000800 126#define NPORT_DMODE0_ZPENAB 0x00001000 127#define NPORT_DMODE0_LISPENAB 0x00002000 128#define NPORT_DMODE0_LISLST 0x00004000 129#define NPORT_DMODE0_L32 0x00008000 130#define NPORT_DMODE0_ZOPQ 0x00010000 131#define NPORT_DMODE0_LISOPQ 0x00020000 132#define NPORT_DMODE0_SHADE 0x00040000 133#define NPORT_DMODE0_LRONLY 0x00080000 134#define NPORT_DMODE0_XYOFF 0x00100000 135#define NPORT_DMODE0_CLAMP 0x00200000 136#define NPORT_DMODE0_ENDPF 0x00400000 137#define NPORT_DMODE0_YSTR 0x00800000 138 139 npireg_t lsmode; /* Mode for line stipple ops */ 140 npireg_t lspattern; /* Pattern for line stipple ops */ 141 npireg_t lspatsave; /* Backup save pattern */ 142 npireg_t zpattern; /* Pixel zpattern */ 143 npireg_t colorback; /* Background color */ 144 npireg_t colorvram; /* Clear color for fast vram */ 145 npireg_t alpharef; /* Reference value for afunctions */ 146 unsigned int pad0; 147 npireg_t smask0x; /* Window GL relative screen mask 0 */ 148 npireg_t smask0y; /* Window GL relative screen mask 0 */ 149 npireg_t _setup; 150 npireg_t _stepz; 151 npireg_t _lsrestore; 152 npireg_t _lssave; 153 154 unsigned int _pad1[0x30]; 155 156 /* Iterators, full state for context switch */ 157 npfreg_t _xstart; /* X-start point (current) */ 158 npfreg_t _ystart; /* Y-start point (current) */ 159 npfreg_t _xend; /* x-end point */ 160 npfreg_t _yend; /* y-end point */ 161 npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */ 162 npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */ 163 npfreg_t bresd; 164 npfreg_t bress1; 165 npireg_t bresoctinc1; 166 volatile int bresrndinc2; 167 npireg_t brese1; 168 npireg_t bress2; 169 npireg_t aweight0; 170 npireg_t aweight1; 171 npfreg_t xstartf; 172 npfreg_t ystartf; 173 npfreg_t xendf; 174 npfreg_t yendf; 175 npireg_t xstarti; 176 npfreg_t xendf1; 177 npireg_t xystarti; 178 npireg_t xyendi; 179 npireg_t xstartendi; 180 181 unsigned int _unused2[0x29]; 182 183 npfreg_t colorred; 184 npfreg_t coloralpha; 185 npfreg_t colorgrn; 186 npfreg_t colorblue; 187 npfreg_t slopered; 188 npfreg_t slopealpha; 189 npfreg_t slopegrn; 190 npfreg_t slopeblue; 191 npireg_t wrmask; 192 npireg_t colori; 193 npfreg_t colorx; 194 npfreg_t slopered1; 195 npireg_t hostrw0; 196 npireg_t hostrw1; 197 npireg_t dcbmode; 198#define NPORT_DMODE_WMASK 0x00000003 199#define NPORT_DMODE_W4 0x00000000 200#define NPORT_DMODE_W1 0x00000001 201#define NPORT_DMODE_W2 0x00000002 202#define NPORT_DMODE_W3 0x00000003 203#define NPORT_DMODE_EDPACK 0x00000004 204#define NPORT_DMODE_ECINC 0x00000008 205#define NPORT_DMODE_CMASK 0x00000070 206#define NPORT_DMODE_AMASK 0x00000780 207#define NPORT_DMODE_AVC2 0x00000000 208#define NPORT_DMODE_ACMALL 0x00000080 209#define NPORT_DMODE_ACM0 0x00000100 210#define NPORT_DMODE_ACM1 0x00000180 211#define NPORT_DMODE_AXMALL 0x00000200 212#define NPORT_DMODE_AXM0 0x00000280 213#define NPORT_DMODE_AXM1 0x00000300 214#define NPORT_DMODE_ABT 0x00000380 215#define NPORT_DMODE_AVCC1 0x00000400 216#define NPORT_DMODE_AVAB1 0x00000480 217#define NPORT_DMODE_ALG3V0 0x00000500 218#define NPORT_DMODE_A1562 0x00000580 219#define NPORT_DMODE_ESACK 0x00000800 220#define NPORT_DMODE_EASACK 0x00001000 221#define NPORT_DMODE_CWMASK 0x0003e000 222#define NPORT_DMODE_CHMASK 0x007c0000 223#define NPORT_DMODE_CSMASK 0x0f800000 224#define NPORT_DMODE_SENDIAN 0x10000000 225 226 unsigned int _unused3; 227 228 union np_dcb dcbdata0; 229 npireg_t dcbdata1; 230}; 231 232struct newport_cregs { 233 npireg_t smask1x; 234 npireg_t smask1y; 235 npireg_t smask2x; 236 npireg_t smask2y; 237 npireg_t smask3x; 238 npireg_t smask3y; 239 npireg_t smask4x; 240 npireg_t smask4y; 241 npireg_t topscan; 242 npireg_t xywin; 243 npireg_t clipmode; 244#define NPORT_CMODE_SM0 0x00000001 245#define NPORT_CMODE_SM1 0x00000002 246#define NPORT_CMODE_SM2 0x00000004 247#define NPORT_CMODE_SM3 0x00000008 248#define NPORT_CMODE_SM4 0x00000010 249#define NPORT_CMODE_CMSK 0x00001e00 250 251 unsigned int _unused0; 252 unsigned int config; 253#define NPORT_CFG_G32MD 0x00000001 254#define NPORT_CFG_BWIDTH 0x00000002 255#define NPORT_CFG_ERCVR 0x00000004 256#define NPORT_CFG_BDMSK 0x00000078 257#define NPORT_CFG_BFAINT 0x00000080 258#define NPORT_CFG_GDMSK 0x00001f80 259#define NPORT_CFG_GD0 0x00000100 260#define NPORT_CFG_GD1 0x00000200 261#define NPORT_CFG_GD2 0x00000400 262#define NPORT_CFG_GD3 0x00000800 263#define NPORT_CFG_GD4 0x00001000 264#define NPORT_CFG_GFAINT 0x00002000 265#define NPORT_CFG_TOMSK 0x0001c000 266#define NPORT_CFG_VRMSK 0x000e0000 267#define NPORT_CFG_FBTYP 0x00100000 268 269 npireg_t _unused1; 270 npireg_t status; 271#define NPORT_STAT_VERS 0x00000007 272#define NPORT_STAT_GBUSY 0x00000008 273#define NPORT_STAT_BBUSY 0x00000010 274#define NPORT_STAT_VRINT 0x00000020 275#define NPORT_STAT_VIDINT 0x00000040 276#define NPORT_STAT_GLMSK 0x00001f80 277#define NPORT_STAT_BLMSK 0x0007e000 278#define NPORT_STAT_BFIRQ 0x00080000 279#define NPORT_STAT_GFIRQ 0x00100000 280 281 npireg_t ustatus; 282 npireg_t dcbreset; 283}; 284 285struct newport_regs { 286 struct newport_rexregs set; 287 unsigned int _unused0[0x16e]; 288 struct newport_rexregs go; 289 unsigned int _unused1[0x22e]; 290 struct newport_cregs cset; 291 unsigned int _unused2[0x1ef]; 292 struct newport_cregs cgo; 293}; 294 295typedef struct { 296 unsigned int drawmode1; 297 unsigned int drawmode0; 298 unsigned int lsmode; 299 unsigned int lspattern; 300 unsigned int lspatsave; 301 unsigned int zpattern; 302 unsigned int colorback; 303 unsigned int colorvram; 304 unsigned int alpharef; 305 unsigned int smask0x; 306 unsigned int smask0y; 307 unsigned int _xstart; 308 unsigned int _ystart; 309 unsigned int _xend; 310 unsigned int _yend; 311 unsigned int xsave; 312 unsigned int xymove; 313 unsigned int bresd; 314 unsigned int bress1; 315 unsigned int bresoctinc1; 316 unsigned int bresrndinc2; 317 unsigned int brese1; 318 unsigned int bress2; 319 320 unsigned int aweight0; 321 unsigned int aweight1; 322 unsigned int colorred; 323 unsigned int coloralpha; 324 unsigned int colorgrn; 325 unsigned int colorblue; 326 unsigned int slopered; 327 unsigned int slopealpha; 328 unsigned int slopegrn; 329 unsigned int slopeblue; 330 unsigned int wrmask; 331 unsigned int hostrw0; 332 unsigned int hostrw1; 333 334 /* configregs */ 335 336 unsigned int smask1x; 337 unsigned int smask1y; 338 unsigned int smask2x; 339 unsigned int smask2y; 340 unsigned int smask3x; 341 unsigned int smask3y; 342 unsigned int smask4x; 343 unsigned int smask4y; 344 unsigned int topscan; 345 unsigned int xywin; 346 unsigned int clipmode; 347 unsigned int config; 348 349 /* dcb registers */ 350 unsigned int dcbmode; 351 unsigned int dcbdata0; 352 unsigned int dcbdata1; 353} newport_ctx; 354 355/* Reading/writing VC2 registers. */ 356#define VC2_REGADDR_INDEX 0x00000000 357#define VC2_REGADDR_IREG 0x00000010 358#define VC2_REGADDR_RAM 0x00000030 359#define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000) 360 361#define VC2_VLINET_ADDR 0x000 362#define VC2_VFRAMET_ADDR 0x400 363#define VC2_CGLYPH_ADDR 0x500 364 365/* Now the Indexed registers of the VC2. */ 366#define VC2_IREG_VENTRY 0x00 367#define VC2_IREG_CENTRY 0x01 368#define VC2_IREG_CURSX 0x02 369#define VC2_IREG_CURSY 0x03 370#define VC2_IREG_CCURSX 0x04 371#define VC2_IREG_DENTRY 0x05 372#define VC2_IREG_SLEN 0x06 373#define VC2_IREG_RADDR 0x07 374#define VC2_IREG_VFPTR 0x08 375#define VC2_IREG_VLSPTR 0x09 376#define VC2_IREG_VLIR 0x0a 377#define VC2_IREG_VLCTR 0x0b 378#define VC2_IREG_CTPTR 0x0c 379#define VC2_IREG_WCURSY 0x0d 380#define VC2_IREG_DFPTR 0x0e 381#define VC2_IREG_DLTPTR 0x0f 382#define VC2_IREG_CONTROL 0x10 383#define VC2_IREG_CONFIG 0x20 384 385static inline void newport_vc2_set(struct newport_regs *regs, 386 unsigned char vc2ireg, 387 unsigned short val) 388{ 389 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 | 390 NPORT_DMODE_ECINC | VC2_PROTOCOL); 391 regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8); 392} 393 394static inline unsigned short newport_vc2_get(struct newport_regs *regs, 395 unsigned char vc2ireg) 396{ 397 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 | 398 NPORT_DMODE_ECINC | VC2_PROTOCOL); 399 regs->set.dcbdata0.bybytes.b3 = vc2ireg; 400 regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 | 401 NPORT_DMODE_ECINC | VC2_PROTOCOL); 402 return regs->set.dcbdata0.byshort.s1; 403} 404 405/* VC2 Control register bits */ 406#define VC2_CTRL_EVIRQ 0x0001 407#define VC2_CTRL_EDISP 0x0002 408#define VC2_CTRL_EVIDEO 0x0004 409#define VC2_CTRL_EDIDS 0x0008 410#define VC2_CTRL_ECURS 0x0010 411#define VC2_CTRL_EGSYNC 0x0020 412#define VC2_CTRL_EILACE 0x0040 413#define VC2_CTRL_ECDISP 0x0080 414#define VC2_CTRL_ECCURS 0x0100 415#define VC2_CTRL_ECG64 0x0200 416#define VC2_CTRL_GLSEL 0x0400 417 418/* Controlling the color map on NEWPORT. */ 419#define NCMAP_REGADDR_AREG 0x00000000 420#define NCMAP_REGADDR_ALO 0x00000000 421#define NCMAP_REGADDR_AHI 0x00000010 422#define NCMAP_REGADDR_PBUF 0x00000020 423#define NCMAP_REGADDR_CREG 0x00000030 424#define NCMAP_REGADDR_SREG 0x00000040 425#define NCMAP_REGADDR_RREG 0x00000060 426#define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000) 427 428static __inline__ void newport_cmap_setaddr(struct newport_regs *regs, 429 unsigned short addr) 430{ 431 regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | 432 NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC | 433 NCMAP_REGADDR_AREG | NPORT_DMODE_W2); 434 regs->set.dcbdata0.byshort.s1 = addr; 435 regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL | 436 NCMAP_REGADDR_PBUF | NPORT_DMODE_W3); 437} 438 439static __inline__ void newport_cmap_setrgb(struct newport_regs *regs, 440 unsigned char red, 441 unsigned char green, 442 unsigned char blue) 443{ 444 regs->set.dcbdata0.byword = 445 (red << 24) | 446 (green << 16) | 447 (blue << 8); 448} 449 450/* Miscellaneous NEWPORT routines. */ 451#define BUSY_TIMEOUT 100000 452static __inline__ int newport_wait(struct newport_regs *regs) 453{ 454 int t = BUSY_TIMEOUT; 455 456 while (--t) 457 if (!(regs->cset.status & NPORT_STAT_GBUSY)) 458 break; 459 return !t; 460} 461 462static __inline__ int newport_bfwait(struct newport_regs *regs) 463{ 464 int t = BUSY_TIMEOUT; 465 466 while (--t) 467 if(!(regs->cset.status & NPORT_STAT_BBUSY)) 468 break; 469 return !t; 470} 471 472/* 473 * DCBMODE register defines: 474 */ 475 476/* Width of the data being transferred for each DCBDATA[01] word */ 477#define DCB_DATAWIDTH_4 0x0 478#define DCB_DATAWIDTH_1 0x1 479#define DCB_DATAWIDTH_2 0x2 480#define DCB_DATAWIDTH_3 0x3 481 482/* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */ 483#define DCB_ENDATAPACK (1 << 2) 484 485/* Enables DCBCRS auto increment after each DCB transfer */ 486#define DCB_ENCRSINC (1 << 3) 487 488/* shift for accessing the control register select address (DBCCRS, 3 bits) */ 489#define DCB_CRS_SHIFT 4 490 491/* DCBADDR (4 bits): display bus slave address */ 492#define DCB_ADDR_SHIFT 7 493#define DCB_VC2 (0 << DCB_ADDR_SHIFT) 494#define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT) 495#define DCB_CMAP0 (2 << DCB_ADDR_SHIFT) 496#define DCB_CMAP1 (3 << DCB_ADDR_SHIFT) 497#define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT) 498#define DCB_XMAP0 (5 << DCB_ADDR_SHIFT) 499#define DCB_XMAP1 (6 << DCB_ADDR_SHIFT) 500#define DCB_BT445 (7 << DCB_ADDR_SHIFT) 501#define DCB_VCC1 (8 << DCB_ADDR_SHIFT) 502#define DCB_VAB1 (9 << DCB_ADDR_SHIFT) 503#define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT) 504#define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT) 505#define DCB_RESERVED (15 << DCB_ADDR_SHIFT) 506 507/* DCB protocol ack types */ 508#define DCB_ENSYNCACK (1 << 11) 509#define DCB_ENASYNCACK (1 << 12) 510 511#define DCB_CSWIDTH_SHIFT 13 512#define DCB_CSHOLD_SHIFT 18 513#define DCB_CSSETUP_SHIFT 23 514 515/* XMAP9 specific defines */ 516/* XMAP9 -- registers as seen on the DCBMODE register*/ 517# define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT) 518# define XM9_PUPMODE (1 << 0) 519# define XM9_ODD_PIXEL (1 << 1) 520# define XM9_8_BITPLANES (1 << 2) 521# define XM9_SLOW_DCB (1 << 3) 522# define XM9_VIDEO_RGBMAP_MASK (3 << 4) 523# define XM9_EXPRESS_VIDEO (1 << 6) 524# define XM9_VIDEO_OPTION (1 << 7) 525# define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT) 526# define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT) 527# define XM9_FIFO_0_AVAIL 0 528# define XM9_FIFO_1_AVAIL 1 529# define XM9_FIFO_2_AVAIL 3 530# define XM9_FIFO_3_AVAIL 2 531# define XM9_FIFO_FULL XM9_FIFO_0_AVAIL 532# define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL 533# define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT) 534# define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT) 535# define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT) 536# define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT) 537 538 539#define DCB_CYCLES(setup,hold,width) \ 540 ((hold << DCB_CSHOLD_SHIFT) | \ 541 (setup << DCB_CSSETUP_SHIFT)| \ 542 (width << DCB_CSWIDTH_SHIFT)) 543 544#define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0) 545#define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0) 546#define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0) 547#define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3) 548 549static __inline__ void 550xmap9FIFOWait (struct newport_regs *rex) 551{ 552 rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL | 553 DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL; 554 newport_bfwait (rex); 555 556 while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY) 557 ; 558} 559 560static __inline__ void 561xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq) 562{ 563 if (cfreq > 119) 564 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | 565 DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL; 566 else if (cfreq > 59) 567 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | 568 DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL; 569 else 570 rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA | 571 DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; 572 rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff); 573} 574 575#define BT445_PROTOCOL DCB_CYCLES(1,1,3) 576 577#define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT) 578#define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT) 579 580#define BT445_REVISION_REG 0x01 581 582#endif /* !(_SGI_NEWPORT_H) */ 583 584