/external/llvm/lib/CodeGen/ |
H A D | PHIEliminationUtils.cpp | 17 // findCopyInsertPoint - Find a safe place in MBB to insert a copy from SrcReg 19 // SrcReg, but before any subsequent point where control flow might jump out of 23 unsigned SrcReg) { 37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg), 22 findPHICopyInsertPoint(MachineBasicBlock* MBB, MachineBasicBlock* SuccMBB, unsigned SrcReg) argument
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H A D | OptimizePHIs.cpp | 99 unsigned SrcReg = MI->getOperand(i).getReg(); local 100 if (SrcReg == DstReg) 102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); 120 SingleValReg = SrcReg;
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H A D | RegisterCoalescer.h | 35 /// SrcReg - the virtual register that will be coalesced into dstReg. 36 unsigned SrcReg; member in class:llvm::CoalescerPair 42 /// SrcIdx - The sub-register index of the old SrcReg in the new coalesced 52 /// Flipped - True when DstReg and SrcReg are reversed from the original 58 /// SrcReg and DstReg. 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible 105 unsigned getSrcReg() const { return SrcReg; } 111 /// getSrcIdx - Return the subregister index that SrcReg wil [all...] |
H A D | PHIElimination.cpp | 295 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); local 298 isImplicitlyDefined(SrcReg, MRI); 299 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && 315 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); 327 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 333 .addReg(SrcReg, 0, SrcSubReg); 352 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]; 356 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) { 366 if (Term->readsRegister(SrcReg)) 380 if (KillInst->readsRegister(SrcReg)) [all...] |
H A D | PeepholeOptimizer.cpp | 144 unsigned SrcReg, DstReg, SubIdx; local 145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 149 TargetRegisterInfo::isPhysicalRegister(SrcReg)) 152 if (MRI->hasOneNonDBGUse(SrcReg)) 163 // The ext instr may be operating on a sub-register of SrcReg as well. 166 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of 167 // SrcReg:SubIdx should be replaced. 169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; 187 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); 199 // Only accept uses of SrcReg 375 unsigned SrcReg, SrcReg2; local [all...] |
H A D | MachineSSAUpdater.cpp | 94 unsigned SrcReg = I->getOperand(i).getReg(); local 96 if (AVals[SrcBB] != SrcReg) {
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H A D | MachineSink.cpp | 129 unsigned SrcReg = MI->getOperand(1).getReg(); local 131 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) || 133 !MRI->hasOneNonDBGUse(SrcReg)) 136 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 141 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 146 MRI->replaceRegWith(DstReg, SrcReg);
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 43 unsigned DestReg, unsigned SrcReg, 46 .addReg(SrcReg, getKillRegState(KillSrc))); 47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && 53 unsigned SrcReg, bool isKill, int FI, 57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 58 isARMLowRegister(SrcReg))) && "Unknown regclass!"); 61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && 62 isARMLowRegister(SrcReg))) { 74 .addReg(SrcReg, getKillRegState(isKill)) 41 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | Thumb2InstrInfo.cpp | 114 unsigned DestReg, unsigned SrcReg, 117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) 118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); 121 .addReg(SrcReg, getKillRegState(KillSrc))); 126 unsigned SrcReg, bool isKill, int FI, 143 .addReg(SrcReg, getKillRegState(isKill)) 148 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI); 112 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 125 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | Thumb2ITBlockPass.cpp | 118 unsigned SrcReg = MI->getOperand(1).getReg(); local 121 if (Uses.count(DstReg) || Defs.count(SrcReg))
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 78 // STriw_pred [R30], ofst, SrcReg; 84 int SrcReg = MI->getOperand(2).getReg(); local 85 assert(Hexagon::PredRegsRegClass.contains(SrcReg) && 96 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 105 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 114 HEXAGON_RESERVED_REG_2).addReg(SrcReg);
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H A D | HexagonPeephole.cpp | 134 unsigned SrcReg = Src.getReg(); local 137 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 141 PeepholeMap[DstReg] = SrcReg; 158 unsigned SrcReg = Src1.getReg(); local 160 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/); 170 unsigned SrcReg = Src.getReg(); local 173 TargetRegisterInfo::isVirtualRegister(SrcReg)) { 177 PeepholeMap[DstReg] = SrcReg; 193 unsigned SrcReg = Src.getReg(); local 195 TargetRegisterInfo::isVirtualRegister(SrcReg)) { [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | Mips16InstrInfo.cpp | 59 unsigned DestReg, unsigned SrcReg, 64 if (Mips::CPURegsRegClass.contains(SrcReg)) 78 if (SrcReg) 79 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 84 unsigned SrcReg, bool isKill, int FI, 57 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 83 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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H A D | MipsSEInstrInfo.cpp | 87 unsigned DestReg, unsigned SrcReg, 92 if (Mips::CPURegsRegClass.contains(SrcReg)) 94 else if (Mips::CCRRegClass.contains(SrcReg)) 96 else if (Mips::FGR32RegClass.contains(SrcReg)) 98 else if (SrcReg == Mips::HI) 99 Opc = Mips::MFHI, SrcReg = 0; 100 else if (SrcReg == Mips::LO) 101 Opc = Mips::MFLO, SrcReg = 0; 103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. 113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 85 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 155 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 329 unsigned SrcReg = I->getOperand(1).getReg(); local [all...] |
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeInstrInfo.cpp | 86 unsigned DestReg, unsigned SrcReg, 89 .addReg(SrcReg, getKillRegState(KillSrc)).addReg(MBlaze::R0); 94 unsigned SrcReg, bool isKill, int FI, 98 BuildMI(MBB, I, DL, get(MBlaze::SWI)).addReg(SrcReg,getKillRegState(isKill)) 84 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 93 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430InstrInfo.cpp | 36 unsigned SrcReg, bool isKill, int FrameIdx, 53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); 90 unsigned DestReg, unsigned SrcReg, 93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) 95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) 101 .addReg(SrcReg, getKillRegState(KillSrc)); 34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 88 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXInstrInfo.cpp | 38 unsigned DestReg, unsigned SrcReg, 41 NVPTX::Int32RegsRegClass.contains(SrcReg)) 43 .addReg(SrcReg, getKillRegState(KillSrc)); 45 NVPTX::Int8RegsRegClass.contains(SrcReg)) 47 .addReg(SrcReg, getKillRegState(KillSrc)); 49 NVPTX::Int1RegsRegClass.contains(SrcReg)) 51 .addReg(SrcReg, getKillRegState(KillSrc)); 53 NVPTX::Float32RegsRegClass.contains(SrcReg)) 55 .addReg(SrcReg, getKillRegState(KillSrc)); 57 NVPTX::Int16RegsRegClass.contains(SrcReg)) 36 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 113 isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DestReg) const argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 304 unsigned SrcReg = ValueMap[V]; local 305 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) { 309 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth); 341 unsigned SrcReg = ValueMap[V]; local 342 if (!TargetRegisterInfo::isVirtualRegister(SrcReg)) { 346 const LiveOutInfo *SrcLOI = GetLiveOutRegInfo(SrcReg, BitWidth);
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H A D | InstrEmitter.cpp | 85 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { 87 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { 92 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 120 } else if (DestReg != SrcReg) 157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 172 VRBase = SrcReg; 177 VRBase).addReg(SrcReg); 485 unsigned SrcReg, DstReg, DefSubIdx; 487 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && 489 TRC == MRI->getRegClass(SrcReg)) { 84 EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) argument [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.cpp | 126 unsigned DestReg, unsigned SrcReg, 135 .addReg(SrcReg, getKillRegState(KillSrc)); 141 unsigned SrcReg, bool isKill, int FrameIdx, 168 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx); 124 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 139 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcInstrInfo.cpp | 282 unsigned DestReg, unsigned SrcReg, 284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) 286 .addReg(SrcReg, getKillRegState(KillSrc)); 287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) 289 .addReg(SrcReg, getKillRegState(KillSrc)); 290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) 292 .addReg(SrcReg, getKillRegState(KillSrc)); 299 unsigned SrcReg, bool isKill, int FI, 305 // On the order of operands here: think "[FrameIdx + 0] = SrcReg". 308 .addReg(SrcReg, getKillRegStat 280 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 298 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreFrameLowering.cpp | 62 unsigned SrcReg, int Offset, DebugLoc dl, 71 .addReg(SrcReg) 60 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
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H A D | XCoreInstrInfo.cpp | 336 unsigned DestReg, unsigned SrcReg, 339 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); 343 .addReg(SrcReg, getKillRegState(KillSrc)) 348 if (GRDest && SrcReg == XCore::SP) { 355 .addReg(SrcReg, getKillRegState(KillSrc)); 363 unsigned SrcReg, bool isKill, 371 .addReg(SrcReg, getKillRegState(isKill)) 334 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 361 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 87 unsigned &SrcReg, unsigned &DstReg, 93 SrcReg = MI.getOperand(1).getReg(); 415 unsigned DestReg, unsigned SrcReg, 418 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) 420 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) 422 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) 424 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) 426 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) 428 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) 436 .addReg(SrcReg) 86 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument 413 copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DestReg, unsigned SrcReg, bool KillSrc) const argument 443 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 587 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | PPCRegisterInfo.cpp | 399 MachineInstr &MI = *II; // ; SPILL_CR <SrcReg>, <offset> 413 unsigned SrcReg = MI.getOperand(0).getReg(); local 416 // an MFCRpsued to save all of the CRBits and, if needed, kill the SrcReg. 418 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 422 if (SrcReg != PPC::CR0) 426 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
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