Searched refs:i64 (Results 1 - 25 of 95) sorted by relevance

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/external/qemu/target-arm/
H A Dhelper.h50 DEF_HELPER_1(logicq_cc, i32, i64)
117 DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr)
118 DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr)
119 DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr)
120 DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr)
125 DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr)
126 DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr)
127 DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr)
128 DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr)
169 DEF_HELPER_2(neon_qadd_u64, i64, i6
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H A Dhelper-android.h6 DEF_HELPER_2(traceBB32, void, i64, i32)
9 DEF_HELPER_2(traceBB64, void, i64, i64)
/external/qemu/target-mips/
H A Dhelper.h170 DEF_HELPER_1(float_cvtd_s, i64, i32)
171 DEF_HELPER_1(float_cvtd_w, i64, i32)
172 DEF_HELPER_1(float_cvtd_l, i64, i64)
173 DEF_HELPER_1(float_cvtl_d, i64, i64)
174 DEF_HELPER_1(float_cvtl_s, i64, i32)
175 DEF_HELPER_1(float_cvtps_pw, i64, i64)
176 DEF_HELPER_1(float_cvtpw_ps, i64, i6
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/external/openssl/crypto/sha/asm/
H A Dsha512-armv4.s463 vadd.i64 d27,d28,d23
469 vadd.i64 d27,d24
471 vadd.i64 d27,d29
477 vadd.i64 d27,d0
484 vadd.i64 d23,d27
485 vadd.i64 d19,d27
486 vadd.i64 d23,d30
500 vadd.i64 d27,d28,d22
506 vadd.i64 d27,d24
508 vadd.i64 d2
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H A Dsha512-armv4.pl470 vadd.i64 $T1,$K,$h
476 vadd.i64 $T1,$t0
478 vadd.i64 $T1,$Ch
484 vadd.i64 $T1,@X[$i%16]
491 vadd.i64 $h,$T1
492 vadd.i64 $d,$T1
493 vadd.i64 $h,$Maj
519 vadd.i64 @X[$i%8],$s1
526 vadd.i64 @X[$i%8],$s0
530 vadd.i64
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/external/stlport/src/
H A Dnum_get_float.cpp39 uint64_t i64; member in union:_ll
490 vv.i64 = 0L;
493 vv.i64 *= 10;
494 vv.i64 += *buffer++;
497 if ( vv.i64 == ULL(0) ) { /* Check for zero and treat it as a special case */
507 if ((vv.i64 >> 32) != 0) { nzero = 32; }
508 if ((vv.i64 >> (16 + nzero)) != 0) { nzero += 16; }
509 if ((vv.i64 >> ( 8 + nzero)) != 0) { nzero += 8; }
510 if ((vv.i64 >> ( 4 + nzero)) != 0) { nzero += 4; }
511 if ((vv.i64 >> (
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/external/clang/test/Sema/
H A Datomic-ops.c42 int __attribute__((vector_size(8))) i64; variable
46 _Static_assert(__atomic_is_lock_free(1, &i64), "");
49 _Static_assert(__atomic_is_lock_free(2, &i64), "");
52 _Static_assert(__atomic_is_lock_free(4, &i64), "");
54 _Static_assert(__atomic_is_lock_free(8, &i64), "");
69 _Static_assert(__atomic_always_lock_free(1, &i64), "");
72 _Static_assert(__atomic_always_lock_free(2, &i64), "");
75 _Static_assert(__atomic_always_lock_free(4, &i64), "");
77 _Static_assert(__atomic_always_lock_free(8, &i64), "");
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp67 /// i64.
69 return CurDAG->getTargetConstant(Imm, MVT::i64);
304 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
350 // Don't even go down this path for i64, since different logic will be
508 } else if (LHS.getValueType() == MVT::i64) {
514 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
518 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
531 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
533 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
540 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LH
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/external/qemu/target-i386/
H A Dhelper.h97 DEF_HELPER_2(svm_check_intercept_param, void, i32, i64)
98 DEF_HELPER_2(vmexit, void, i32, i64)
112 DEF_HELPER_1(fldl_FT0, void, i64)
115 DEF_HELPER_1(fldl_ST0, void, i64)
119 DEF_HELPER_0(fstl_ST0, i64)
/external/llvm/lib/Target/Hexagon/
H A DHexagonVarargsCallingConvention.h39 (MVT(MVT::i64).getSizeInBits() / 8))) {
63 if (LocVT == MVT::i64 ||
119 if (LocVT == MVT::i64 ||
H A DHexagonISelLowering.cpp111 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
150 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
225 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
252 if (LocVT == MVT::i64 || LocVT == MVT::f64) {
598 if (VT == MVT::i64 || VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
644 if (ST->getValue().getValueType() == MVT::i64 && ST->isTruncatingStore()) {
852 } else if (RegVT == MVT::i64) {
1041 addRegisterClass(MVT::i64, &Hexagon::DoubleRegsRegClass);
1078 setOperationAction(ISD::SDIV, MVT::i64, Expand);
1080 setOperationAction(ISD::SREM, MVT::i64, Expan
[all...]
/external/openssl/crypto/modes/
H A Dmodes_lcl.h12 typedef __int64 i64; typedef
16 typedef long i64; typedef
20 typedef long long i64; typedef
/external/llvm/test/MC/ARM/
H A Dneon-sub-encoding.s6 vsub.i64 d16, d17, d16
11 vsub.i64 q8, q8, q9
17 vsub.i64 d16, d24
22 vsub.i64 q4, q7
28 @ CHECK: vsub.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf3]
33 @ CHECK: vsub.i64 q8, q8, q9 @ encoding: [0xe2,0x08,0x70,0xf3]
39 @ CHECK: vsub.i64 d16, d16, d24 @ encoding: [0xa8,0x08,0x70,0xf3]
44 @ CHECK: vsub.i64 q4, q4, q7 @ encoding: [0x4e,0x88,0x38,0xf3]
127 @ CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2]
128 vsubhn.i64 d1
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H A Dneont2-shift-encoding.s19 @ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xff,0xef,0xb0,0x05]
20 vshl.i64 d16, d16, #63
35 @ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xff,0xef,0xf0,0x05]
36 vshl.i64 q8, q8, #63
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
161 @ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x70,0x08]
162 vrshrn.i64 d16, q8, #32
H A Dneon-mov-encoding.s12 vmov.i64 d16, #0xFF0000FF0000FFFF
23 @ CHECK: vmov.i64 d16, #0xff0000ff0000ffff @ encoding: [0x33,0x0e,0xc1,0xf3]
36 vmov.i64 q8, #0xFF0000FF0000FFFF
47 @ CHECK: vmov.i64 q8, #0xff0000ff0000ffff @ encoding: [0x73,0x0e,0xc1,0xf3]
84 vmovn.i64 d16, q8
97 @ CHECK: vmovn.i64 d16, q8 @ encoding: [0x20,0x02,0xfa,0xf3]
/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp108 addRegisterClass(MVT::i64, &SPU::R64CRegClass);
121 setTruncStoreAction(MVT::i128, MVT::i64, Expand);
171 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
196 setOperationAction(ISD::SREM, MVT::i64, Expand);
197 setOperationAction(ISD::UREM, MVT::i64, Expand);
198 setOperationAction(ISD::SDIV, MVT::i64, Expand);
199 setOperationAction(ISD::UDIV, MVT::i64, Expand);
200 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
201 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
247 setOperationAction(ISD::SHL, MVT::i64, Lega
[all...]
H A DSPUISelDAGToDAG.cpp189 ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
190 (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
191 (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) {
226 //! Emit the instruction sequence for i64 shl
229 //! Emit the instruction sequence for i64 srl
232 //! Emit the instruction sequence for i64 sra
235 //! Emit the necessary sequence for loading i64 constants:
238 //! Alternate instruction emit sequence for loading i64 constants
584 case MVT::i64:
634 } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
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/external/icu4c/test/iotest/
H A Diotest.cpp213 int64_t i64; local
277 i64 = uto64(argument);
278 uBufferLenReturned = u_sprintf_u(uBuffer, format, i64);
279 uFileBufferLenReturned = u_fprintf_u(testFile.getAlias(), format, i64);
378 int64_t i64, expected64; local
468 uBufferLenReturned = u_sscanf_u(argument, format, &i64);
469 //uFileBufferLenReturned = u_fscanf_u(testFile, format, i64);
470 if (i64 != expected64) {
582 int64_t i64; local
633 i64
[all...]
/external/llvm/test/Bindings/Ocaml/
H A Dvmcore.ml95 (* RUN: grep "const_sext_int.*i64.*-1" < %t.ll
102 (* RUN: grep "const_zext_int64.*i64.*4294967295" < %t.ll
190 (* RUN: grep "const_pointer_null = global i64\* null" < %t.ll
205 (* RUN: grep "@const_neg = global i64 sub" < %t.ll
206 * RUN: grep "@const_nsw_neg = global i64 sub nsw " < %t.ll
207 * RUN: grep "@const_nuw_neg = global i64 sub nuw " < %t.ll
209 * RUN: grep "@const_not = global i64 xor " < %t.ll
210 * RUN: grep "@const_add = global i64 add " < %t.ll
211 * RUN: grep "@const_nsw_add = global i64 add nsw " < %t.ll
212 * RUN: grep "@const_nuw_add = global i64 ad
[all...]
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/jcajce/provider/asymmetric/dh/
H A DKeyAgreementSpi.java39 Integer i64 = Integer.valueOf(64);
45 algorithms.put("DES", i64);
/external/chromium/base/win/
H A Dscoped_variant.h100 void Set(int64 i64);
/external/llvm/include/llvm/Support/
H A DDataTypes.h165 # define INT64_C(C) C##i64
/external/llvm/lib/Target/X86/
H A DX86SelectionDAGInfo.cpp105 AVT = MVT::i64;
151 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));
152 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :
215 AVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
/external/qemu/
H A Ddef-helper.h7 (i32, i64 and ptr). Additional aliases are provided for convenience and
31 #define dh_alias_i64 i64
32 #define dh_alias_s64 i64
34 #define dh_alias_f64 i64
38 #define dh_alias_tl i64
/external/icu4c/test/intltest/
H A Dwinnmtst.cpp236 int64_t i64 = randomInt64(); local
242 getWindowsFormat(lcid, currency, w6Buffer, L"%I64d", i64);
260 wnf->format(i64, u6Buffer);

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