1/****************************************************************************
2 ****************************************************************************
3 ***
4 ***   This header was automatically generated from a Linux kernel header
5 ***   of the same name, to make information necessary for userspace to
6 ***   call into the kernel available to libc.  It contains only constants,
7 ***   structures, and macros generated from the original header, and thus,
8 ***   contains no copyrightable information.
9 ***
10 ***   To edit the content of this header, modify the corresponding
11 ***   source file (e.g. under external/kernel-headers/original/) then
12 ***   run bionic/libc/kernel/tools/update_all.py
13 ***
14 ***   Any manual change here will be lost the next time this script will
15 ***   be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _ASM_DMA_H
20#define _ASM_DMA_H
21#include <asm/io.h>
22#include <linux/spinlock.h>
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#include <linux/delay.h>
25#include <asm/system.h>
26#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
27#define dma_outb outb_p
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#else
30#define dma_outb outb
31#endif
32#define dma_inb inb
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define MAX_DMA_CHANNELS 8
35#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
36#define MAX_DMA_PFN PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
37#define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define IO_DMA1_BASE 0x00
40#define IO_DMA2_BASE 0xC0
41#define DMA1_CMD_REG 0x08
42#define DMA1_STAT_REG 0x08
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define DMA1_REQ_REG 0x09
45#define DMA1_MASK_REG 0x0A
46#define DMA1_MODE_REG 0x0B
47#define DMA1_CLEAR_FF_REG 0x0C
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define DMA1_TEMP_REG 0x0D
50#define DMA1_RESET_REG 0x0D
51#define DMA1_CLR_MASK_REG 0x0E
52#define DMA1_MASK_ALL_REG 0x0F
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54#define DMA2_CMD_REG 0xD0
55#define DMA2_STAT_REG 0xD0
56#define DMA2_REQ_REG 0xD2
57#define DMA2_MASK_REG 0xD4
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define DMA2_MODE_REG 0xD6
60#define DMA2_CLEAR_FF_REG 0xD8
61#define DMA2_TEMP_REG 0xDA
62#define DMA2_RESET_REG 0xDA
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define DMA2_CLR_MASK_REG 0xDC
65#define DMA2_MASK_ALL_REG 0xDE
66#define DMA_ADDR_0 0x00
67#define DMA_ADDR_1 0x02
68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
69#define DMA_ADDR_2 0x04
70#define DMA_ADDR_3 0x06
71#define DMA_ADDR_4 0xC0
72#define DMA_ADDR_5 0xC4
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define DMA_ADDR_6 0xC8
75#define DMA_ADDR_7 0xCC
76#define DMA_CNT_0 0x01
77#define DMA_CNT_1 0x03
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define DMA_CNT_2 0x05
80#define DMA_CNT_3 0x07
81#define DMA_CNT_4 0xC2
82#define DMA_CNT_5 0xC6
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define DMA_CNT_6 0xCA
85#define DMA_CNT_7 0xCE
86#define DMA_PAGE_0 0x87
87#define DMA_PAGE_1 0x83
88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
89#define DMA_PAGE_2 0x81
90#define DMA_PAGE_3 0x82
91#define DMA_PAGE_5 0x8B
92#define DMA_PAGE_6 0x89
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94#define DMA_PAGE_7 0x8A
95#define DMA_MODE_READ 0x44
96#define DMA_MODE_WRITE 0x48
97#define DMA_MODE_CASCADE 0xC0
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99#define DMA_AUTOINIT 0x10
100#define isa_dma_bridge_buggy (0)
101#endif
102