1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995 Waldorf GmbH 7 * Copyright (C) 1994 - 2000, 06 Ralf Baechle 8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc. 9 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved. 10 * Author: Maciej W. Rozycki <macro@mips.com> 11 */ 12#ifndef _ASM_IO_H 13#define _ASM_IO_H 14 15#include <linux/compiler.h> 16#include <linux/kernel.h> 17#include <linux/types.h> 18 19#include <asm/addrspace.h> 20#include <asm/byteorder.h> 21#include <asm/cpu.h> 22#include <asm/cpu-features.h> 23#include <asm-generic/iomap.h> 24#include <asm/page.h> 25#include <asm/pgtable-bits.h> 26#include <asm/processor.h> 27#include <asm/string.h> 28 29#include <ioremap.h> 30#include <mangle-port.h> 31 32/* 33 * Slowdown I/O port space accesses for antique hardware. 34 */ 35#undef CONF_SLOWDOWN_IO 36 37/* 38 * Raw operations are never swapped in software. OTOH values that raw 39 * operations are working on may or may not have been swapped by the bus 40 * hardware. An example use would be for flash memory that's used for 41 * execute in place. 42 */ 43# define __raw_ioswabb(a, x) (x) 44# define __raw_ioswabw(a, x) (x) 45# define __raw_ioswabl(a, x) (x) 46# define __raw_ioswabq(a, x) (x) 47# define ____raw_ioswabq(a, x) (x) 48 49/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */ 50 51#define IO_SPACE_LIMIT 0xffff 52 53/* 54 * On MIPS I/O ports are memory mapped, so we access them using normal 55 * load/store instructions. mips_io_port_base is the virtual address to 56 * which all ports are being mapped. For sake of efficiency some code 57 * assumes that this is an address that can be loaded with a single lui 58 * instruction, so the lower 16 bits must be zero. Should be true on 59 * on any sane architecture; generic code does not use this assumption. 60 */ 61extern const unsigned long mips_io_port_base; 62 63/* 64 * Gcc will generate code to load the value of mips_io_port_base after each 65 * function call which may be fairly wasteful in some cases. So we don't 66 * play quite by the book. We tell gcc mips_io_port_base is a long variable 67 * which solves the code generation issue. Now we need to violate the 68 * aliasing rules a little to make initialization possible and finally we 69 * will need the barrier() to fight side effects of the aliasing chat. 70 * This trickery will eventually collapse under gcc's optimizer. Oh well. 71 */ 72static inline void set_io_port_base(unsigned long base) 73{ 74 * (unsigned long *) &mips_io_port_base = base; 75 barrier(); 76} 77 78/* 79 * Thanks to James van Artsdalen for a better timing-fix than 80 * the two short jumps: using outb's to a nonexistent port seems 81 * to guarantee better timings even on fast machines. 82 * 83 * On the other hand, I'd like to be sure of a non-existent port: 84 * I feel a bit unsafe about using 0x80 (should be safe, though) 85 * 86 * Linus 87 * 88 */ 89 90#define __SLOW_DOWN_IO \ 91 __asm__ __volatile__( \ 92 "sb\t$0,0x80(%0)" \ 93 : : "r" (mips_io_port_base)); 94 95#ifdef CONF_SLOWDOWN_IO 96#ifdef REALLY_SLOW_IO 97#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; } 98#else 99#define SLOW_DOWN_IO __SLOW_DOWN_IO 100#endif 101#else 102#define SLOW_DOWN_IO 103#endif 104 105/* 106 * virt_to_phys - map virtual addresses to physical 107 * @address: address to remap 108 * 109 * The returned physical address is the physical (CPU) mapping for 110 * the memory address given. It is only valid to use this function on 111 * addresses directly mapped or allocated via kmalloc. 112 * 113 * This function does not give bus mappings for DMA transfers. In 114 * almost all conceivable cases a device driver should not be using 115 * this function 116 */ 117static inline unsigned long virt_to_phys(volatile const void *address) 118{ 119 return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; 120} 121 122/* 123 * phys_to_virt - map physical address to virtual 124 * @address: address to remap 125 * 126 * The returned virtual address is a current CPU mapping for 127 * the memory address given. It is only valid to use this function on 128 * addresses that have a kernel mapping 129 * 130 * This function does not handle bus mappings for DMA transfers. In 131 * almost all conceivable cases a device driver should not be using 132 * this function 133 */ 134static inline void * phys_to_virt(unsigned long address) 135{ 136 return (void *)(address + PAGE_OFFSET - PHYS_OFFSET); 137} 138 139/* 140 * ISA I/O bus memory addresses are 1:1 with the physical address. 141 */ 142static inline unsigned long isa_virt_to_bus(volatile void * address) 143{ 144 return (unsigned long)address - PAGE_OFFSET; 145} 146 147static inline void * isa_bus_to_virt(unsigned long address) 148{ 149 return (void *)(address + PAGE_OFFSET); 150} 151 152#define isa_page_to_bus page_to_phys 153 154/* 155 * However PCI ones are not necessarily 1:1 and therefore these interfaces 156 * are forbidden in portable PCI drivers. 157 * 158 * Allow them for x86 for legacy drivers, though. 159 */ 160#define virt_to_bus virt_to_phys 161#define bus_to_virt phys_to_virt 162 163/* 164 * Change "struct page" to physical address. 165 */ 166#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT) 167 168extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags); 169extern void __iounmap(const volatile void __iomem *addr); 170 171static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size, 172 unsigned long flags) 173{ 174 void __iomem *addr = plat_ioremap(offset, size, flags); 175 176 if (addr) 177 return addr; 178 179#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL)) 180 181 if (cpu_has_64bit_addresses) { 182 u64 base = UNCAC_BASE; 183 184 /* 185 * R10000 supports a 2 bit uncached attribute therefore 186 * UNCAC_BASE may not equal IO_BASE. 187 */ 188 if (flags == _CACHE_UNCACHED) 189 base = (u64) IO_BASE; 190 return (void __iomem *) (unsigned long) (base + offset); 191 } else if (__builtin_constant_p(offset) && 192 __builtin_constant_p(size) && __builtin_constant_p(flags)) { 193 phys_t phys_addr, last_addr; 194 195 phys_addr = fixup_bigphys_addr(offset, size); 196 197 /* Don't allow wraparound or zero size. */ 198 last_addr = phys_addr + size - 1; 199 if (!size || last_addr < phys_addr) 200 return NULL; 201 202 /* 203 * Map uncached objects in the low 512MB of address 204 * space using KSEG1. 205 */ 206 if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) && 207 flags == _CACHE_UNCACHED) 208 return (void __iomem *) 209 (unsigned long)CKSEG1ADDR(phys_addr); 210 } 211 212 return __ioremap(offset, size, flags); 213 214#undef __IS_LOW512 215} 216 217/* 218 * ioremap - map bus memory into CPU space 219 * @offset: bus address of the memory 220 * @size: size of the resource to map 221 * 222 * ioremap performs a platform specific sequence of operations to 223 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 224 * writew/writel functions and the other mmio helpers. The returned 225 * address is not guaranteed to be usable directly as a virtual 226 * address. 227 */ 228#define ioremap(offset, size) \ 229 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 230 231/* 232 * ioremap_nocache - map bus memory into CPU space 233 * @offset: bus address of the memory 234 * @size: size of the resource to map 235 * 236 * ioremap_nocache performs a platform specific sequence of operations to 237 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 238 * writew/writel functions and the other mmio helpers. The returned 239 * address is not guaranteed to be usable directly as a virtual 240 * address. 241 * 242 * This version of ioremap ensures that the memory is marked uncachable 243 * on the CPU as well as honouring existing caching rules from things like 244 * the PCI bus. Note that there are other caches and buffers on many 245 * busses. In paticular driver authors should read up on PCI writes 246 * 247 * It's useful if some control registers are in such an area and 248 * write combining or read caching is not desirable: 249 */ 250#define ioremap_nocache(offset, size) \ 251 __ioremap_mode((offset), (size), _CACHE_UNCACHED) 252 253/* 254 * ioremap_cachable - map bus memory into CPU space 255 * @offset: bus address of the memory 256 * @size: size of the resource to map 257 * 258 * ioremap_nocache performs a platform specific sequence of operations to 259 * make bus memory CPU accessible via the readb/readw/readl/writeb/ 260 * writew/writel functions and the other mmio helpers. The returned 261 * address is not guaranteed to be usable directly as a virtual 262 * address. 263 * 264 * This version of ioremap ensures that the memory is marked cachable by 265 * the CPU. Also enables full write-combining. Useful for some 266 * memory-like regions on I/O busses. 267 */ 268#define ioremap_cachable(offset, size) \ 269 __ioremap_mode((offset), (size), _page_cachable_default) 270 271/* 272 * These two are MIPS specific ioremap variant. ioremap_cacheable_cow 273 * requests a cachable mapping, ioremap_uncached_accelerated requests a 274 * mapping using the uncached accelerated mode which isn't supported on 275 * all processors. 276 */ 277#define ioremap_cacheable_cow(offset, size) \ 278 __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) 279#define ioremap_uncached_accelerated(offset, size) \ 280 __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) 281 282static inline void iounmap(const volatile void __iomem *addr) 283{ 284 if (plat_iounmap(addr)) 285 return; 286 287#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1) 288 289 if (cpu_has_64bit_addresses || 290 (__builtin_constant_p(addr) && __IS_KSEG1(addr))) 291 return; 292 293 __iounmap(addr); 294 295#undef __IS_KSEG1 296} 297 298#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 299 \ 300static inline void pfx##write##bwlq(type val, \ 301 volatile void __iomem *mem) \ 302{ \ 303 volatile type *__mem; \ 304 type __val; \ 305 \ 306 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 307 \ 308 __val = pfx##ioswab##bwlq(__mem, val); \ 309 \ 310 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 311 *__mem = __val; \ 312 else if (cpu_has_64bits) { \ 313 unsigned long __flags; \ 314 type __tmp; \ 315 \ 316 if (irq) \ 317 local_irq_save(__flags); \ 318 __asm__ __volatile__( \ 319 ".set mips3" "\t\t# __writeq""\n\t" \ 320 "dsll32 %L0, %L0, 0" "\n\t" \ 321 "dsrl32 %L0, %L0, 0" "\n\t" \ 322 "dsll32 %M0, %M0, 0" "\n\t" \ 323 "or %L0, %L0, %M0" "\n\t" \ 324 "sd %L0, %2" "\n\t" \ 325 ".set mips0" "\n" \ 326 : "=r" (__tmp) \ 327 : "0" (__val), "m" (*__mem)); \ 328 if (irq) \ 329 local_irq_restore(__flags); \ 330 } else \ 331 BUG(); \ 332} \ 333 \ 334static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ 335{ \ 336 volatile type *__mem; \ 337 type __val; \ 338 \ 339 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 340 \ 341 if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \ 342 __val = *__mem; \ 343 else if (cpu_has_64bits) { \ 344 unsigned long __flags; \ 345 \ 346 if (irq) \ 347 local_irq_save(__flags); \ 348 __asm__ __volatile__( \ 349 ".set mips3" "\t\t# __readq" "\n\t" \ 350 "ld %L0, %1" "\n\t" \ 351 "dsra32 %M0, %L0, 0" "\n\t" \ 352 "sll %L0, %L0, 0" "\n\t" \ 353 ".set mips0" "\n" \ 354 : "=r" (__val) \ 355 : "m" (*__mem)); \ 356 if (irq) \ 357 local_irq_restore(__flags); \ 358 } else { \ 359 __val = 0; \ 360 BUG(); \ 361 } \ 362 \ 363 return pfx##ioswab##bwlq(__mem, __val); \ 364} 365 366#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \ 367 \ 368static inline void pfx##out##bwlq##p(type val, unsigned long port) \ 369{ \ 370 volatile type *__addr; \ 371 type __val; \ 372 \ 373 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 374 \ 375 __val = pfx##ioswab##bwlq(__addr, val); \ 376 \ 377 /* Really, we want this to be atomic */ \ 378 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 379 \ 380 *__addr = __val; \ 381 slow; \ 382} \ 383 \ 384static inline type pfx##in##bwlq##p(unsigned long port) \ 385{ \ 386 volatile type *__addr; \ 387 type __val; \ 388 \ 389 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 390 \ 391 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \ 392 \ 393 __val = *__addr; \ 394 slow; \ 395 \ 396 return pfx##ioswab##bwlq(__addr, __val); \ 397} 398 399#define __BUILD_MEMORY_PFX(bus, bwlq, type) \ 400 \ 401__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1) 402 403#define BUILDIO_MEM(bwlq, type) \ 404 \ 405__BUILD_MEMORY_PFX(__raw_, bwlq, type) \ 406__BUILD_MEMORY_PFX(, bwlq, type) \ 407__BUILD_MEMORY_PFX(__mem_, bwlq, type) \ 408 409BUILDIO_MEM(b, u8) 410BUILDIO_MEM(w, u16) 411BUILDIO_MEM(l, u32) 412BUILDIO_MEM(q, u64) 413 414#define __BUILD_IOPORT_PFX(bus, bwlq, type) \ 415 __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \ 416 __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO) 417 418#define BUILDIO_IOPORT(bwlq, type) \ 419 __BUILD_IOPORT_PFX(, bwlq, type) \ 420 __BUILD_IOPORT_PFX(__mem_, bwlq, type) 421 422BUILDIO_IOPORT(b, u8) 423BUILDIO_IOPORT(w, u16) 424BUILDIO_IOPORT(l, u32) 425#ifdef CONFIG_64BIT 426BUILDIO_IOPORT(q, u64) 427#endif 428 429#define __BUILDIO(bwlq, type) \ 430 \ 431__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0) 432 433__BUILDIO(q, u64) 434 435#define readb_relaxed readb 436#define readw_relaxed readw 437#define readl_relaxed readl 438#define readq_relaxed readq 439 440/* 441 * Some code tests for these symbols 442 */ 443#define readq readq 444#define writeq writeq 445 446#define __BUILD_MEMORY_STRING(bwlq, type) \ 447 \ 448static inline void writes##bwlq(volatile void __iomem *mem, \ 449 const void *addr, unsigned int count) \ 450{ \ 451 const volatile type *__addr = addr; \ 452 \ 453 while (count--) { \ 454 __mem_write##bwlq(*__addr, mem); \ 455 __addr++; \ 456 } \ 457} \ 458 \ 459static inline void reads##bwlq(volatile void __iomem *mem, void *addr, \ 460 unsigned int count) \ 461{ \ 462 volatile type *__addr = addr; \ 463 \ 464 while (count--) { \ 465 *__addr = __mem_read##bwlq(mem); \ 466 __addr++; \ 467 } \ 468} 469 470#define __BUILD_IOPORT_STRING(bwlq, type) \ 471 \ 472static inline void outs##bwlq(unsigned long port, const void *addr, \ 473 unsigned int count) \ 474{ \ 475 const volatile type *__addr = addr; \ 476 \ 477 while (count--) { \ 478 __mem_out##bwlq(*__addr, port); \ 479 __addr++; \ 480 } \ 481} \ 482 \ 483static inline void ins##bwlq(unsigned long port, void *addr, \ 484 unsigned int count) \ 485{ \ 486 volatile type *__addr = addr; \ 487 \ 488 while (count--) { \ 489 *__addr = __mem_in##bwlq(port); \ 490 __addr++; \ 491 } \ 492} 493 494#define BUILDSTRING(bwlq, type) \ 495 \ 496__BUILD_MEMORY_STRING(bwlq, type) \ 497__BUILD_IOPORT_STRING(bwlq, type) 498 499BUILDSTRING(b, u8) 500BUILDSTRING(w, u16) 501BUILDSTRING(l, u32) 502#ifdef CONFIG_64BIT 503BUILDSTRING(q, u64) 504#endif 505 506 507/* Depends on MIPS II instruction set */ 508#define mmiowb() asm volatile ("sync" ::: "memory") 509 510static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 511{ 512 memset((void __force *) addr, val, count); 513} 514static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count) 515{ 516 memcpy(dst, (void __force *) src, count); 517} 518static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count) 519{ 520 memcpy((void __force *) dst, src, count); 521} 522 523/* 524 * The caches on some architectures aren't dma-coherent and have need to 525 * handle this in software. There are three types of operations that 526 * can be applied to dma buffers. 527 * 528 * - dma_cache_wback_inv(start, size) makes caches and coherent by 529 * writing the content of the caches back to memory, if necessary. 530 * The function also invalidates the affected part of the caches as 531 * necessary before DMA transfers from outside to memory. 532 * - dma_cache_wback(start, size) makes caches and coherent by 533 * writing the content of the caches back to memory, if necessary. 534 * The function also invalidates the affected part of the caches as 535 * necessary before DMA transfers from outside to memory. 536 * - dma_cache_inv(start, size) invalidates the affected parts of the 537 * caches. Dirty lines of the caches may be written back or simply 538 * be discarded. This operation is necessary before dma operations 539 * to the memory. 540 * 541 * This API used to be exported; it now is for arch code internal use only. 542 */ 543#ifdef CONFIG_DMA_NONCOHERENT 544 545extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size); 546extern void (*_dma_cache_wback)(unsigned long start, unsigned long size); 547extern void (*_dma_cache_inv)(unsigned long start, unsigned long size); 548 549#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start, size) 550#define dma_cache_wback(start, size) _dma_cache_wback(start, size) 551#define dma_cache_inv(start, size) _dma_cache_inv(start, size) 552 553#else /* Sane hardware */ 554 555#define dma_cache_wback_inv(start,size) \ 556 do { (void) (start); (void) (size); } while (0) 557#define dma_cache_wback(start,size) \ 558 do { (void) (start); (void) (size); } while (0) 559#define dma_cache_inv(start,size) \ 560 do { (void) (start); (void) (size); } while (0) 561 562#endif /* CONFIG_DMA_NONCOHERENT */ 563 564/* 565 * Read a 32-bit register that requires a 64-bit read cycle on the bus. 566 * Avoid interrupt mucking, just adjust the address for 4-byte access. 567 * Assume the addresses are 8-byte aligned. 568 */ 569#ifdef __MIPSEB__ 570#define __CSR_32_ADJUST 4 571#else 572#define __CSR_32_ADJUST 0 573#endif 574 575#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v)) 576#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST)) 577 578/* 579 * Convert a physical pointer to a virtual kernel pointer for /dev/mem 580 * access 581 */ 582#define xlate_dev_mem_ptr(p) __va(p) 583 584/* 585 * Convert a virtual cached pointer to an uncached pointer 586 */ 587#define xlate_dev_kmem_ptr(p) p 588 589#endif /* _ASM_IO_H */ 590