1#if !defined (__QEMU_MIPS_DEFS_H__) 2#define __QEMU_MIPS_DEFS_H__ 3 4/* If we want to use host float regs... */ 5//#define USE_HOST_FLOAT_REGS 6 7/* Real pages are variable size... */ 8#define TARGET_PAGE_BITS 12 9#define MIPS_TLB_MAX 128 10 11#if defined(TARGET_MIPS64) 12#define TARGET_LONG_BITS 64 13#else 14#define TARGET_LONG_BITS 32 15#endif 16 17/* Masks used to mark instructions to indicate which ISA level they 18 were introduced in. */ 19#define ISA_MIPS1 0x00000001 20#define ISA_MIPS2 0x00000002 21#define ISA_MIPS3 0x00000004 22#define ISA_MIPS4 0x00000008 23#define ISA_MIPS5 0x00000010 24#define ISA_MIPS32 0x00000020 25#define ISA_MIPS32R2 0x00000040 26#define ISA_MIPS64 0x00000080 27#define ISA_MIPS64R2 0x00000100 28 29/* MIPS ASEs. */ 30#define ASE_MIPS16 0x00001000 31#define ASE_MIPS3D 0x00002000 32#define ASE_MDMX 0x00004000 33#define ASE_DSP 0x00008000 34#define ASE_DSPR2 0x00010000 35#define ASE_MT 0x00020000 36#define ASE_SMARTMIPS 0x00040000 37 38/* Chip specific instructions. */ 39#define INSN_VR54XX 0x80000000 40 41/* MIPS CPU defines. */ 42#define CPU_MIPS1 (ISA_MIPS1) 43#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) 44#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) 45#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) 46#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) 47 48#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) 49 50/* MIPS Technologies "Release 1" */ 51#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) 52#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) 53 54/* MIPS Technologies "Release 2" */ 55#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) 56#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) 57 58/* Strictly follow the architecture standard: 59 - Disallow "special" instruction handling for PMON/SPIM. 60 Note that we still maintain Count/Compare to match the host clock. */ 61//#define MIPS_STRICT_STANDARD 1 62 63#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ 64