1409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if !defined (__QEMU_MIPS_DEFS_H__) 2409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define __QEMU_MIPS_DEFS_H__ 3409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 4409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* If we want to use host float regs... */ 5409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli//#define USE_HOST_FLOAT_REGS 6409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 7409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Real pages are variable size... */ 8409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define TARGET_PAGE_BITS 12 9409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define MIPS_TLB_MAX 128 10409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 11409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#if defined(TARGET_MIPS64) 12409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define TARGET_LONG_BITS 64 13409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#else 14409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define TARGET_LONG_BITS 32 15409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif 16409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 17409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Masks used to mark instructions to indicate which ISA level they 18409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli were introduced in. */ 19409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS1 0x00000001 20409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS2 0x00000002 21409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS3 0x00000004 22409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS4 0x00000008 23409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS5 0x00000010 24409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS32 0x00000020 25409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS32R2 0x00000040 26409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS64 0x00000080 27409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ISA_MIPS64R2 0x00000100 28409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 29409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MIPS ASEs. */ 30409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_MIPS16 0x00001000 31409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_MIPS3D 0x00002000 32409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_MDMX 0x00004000 33409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_DSP 0x00008000 34409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_DSPR2 0x00010000 35409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_MT 0x00020000 36409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define ASE_SMARTMIPS 0x00040000 37409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 38409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Chip specific instructions. */ 39409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define INSN_VR54XX 0x80000000 40409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 41409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MIPS CPU defines. */ 42409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS1 (ISA_MIPS1) 43409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS2 (CPU_MIPS1 | ISA_MIPS2) 44409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) 45409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) 46409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) 47409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 48409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) 49409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 50409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MIPS Technologies "Release 1" */ 51409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS32 (CPU_MIPS2 | ISA_MIPS32) 52409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS64 (CPU_MIPS5 | CPU_MIPS32 | ISA_MIPS64) 53409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 54409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* MIPS Technologies "Release 2" */ 55409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS32R2 (CPU_MIPS32 | ISA_MIPS32R2) 56409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#define CPU_MIPS64R2 (CPU_MIPS64 | CPU_MIPS32R2 | ISA_MIPS64R2) 57409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 58409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli/* Strictly follow the architecture standard: 59409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli - Disallow "special" instruction handling for PMON/SPIM. 60409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli Note that we still maintain Count/Compare to match the host clock. */ 61409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli//#define MIPS_STRICT_STANDARD 1 62409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli 63409c7b66435cf5947cab6bf0710f92507317f22eBhanu Chetlapalli#endif /* !defined (__QEMU_MIPS_DEFS_H__) */ 64