Searched defs:Ins (Results 1 - 23 of 23) sorted by relevance

/external/llvm/lib/Transforms/IPO/
H A DIPConstantPropagation.cpp250 Instruction *Ins = cast<Instruction>(*I); local
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
H A DPartialInlining.cpp93 BasicBlock::iterator Ins = newReturnBlock->begin(); local
98 PHINode* retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
100 Ins = newReturnBlock->getFirstNonPHI();
/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp69 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
71 unsigned NumArgs = Ins.size();
74 MVT ArgVT = Ins[i].VT;
75 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
157 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
159 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
160 MVT VT = Ins[i].VT;
161 ISD::ArgFlagsTy Flags = Ins[i].Flags;
H A DRegAllocGreedy.cpp693 unsigned Ins = 0; local
698 BC.Entry = SpillPlacement::MustSpill, ++Ins; local
700 BC.Entry = SpillPlacement::PrefSpill, ++Ins; local
702 ++Ins;
708 BC.Exit = SpillPlacement::MustSpill, ++Ins; local
710 BC.Exit = SpillPlacement::PrefSpill, ++Ins; local
712 ++Ins;
716 if (Ins)
717 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
904 unsigned Ins
[all...]
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.h89 Ins enumerator in enum:llvm::MipsISD::NodeType
123 const SmallVectorImpl<ISD::InputArg> &Ins,
145 const SmallVectorImpl<ISD::InputArg> &Ins,
155 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMipsISelLowering.cpp78 case MipsISD::Ins: return "MipsISD::Ins";
630 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
1912 const SmallVectorImpl<ISD::InputArg> &Ins,
2165 Ins, dl, DAG, InVals);
2173 const SmallVectorImpl<ISD::InputArg> &Ins,
2181 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
2228 &Ins,
2247 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32);
2249 CCInfo.AnalyzeFormalArguments(Ins, CC_Mip
1907 LowerCall(SDValue InChain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2171 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2224 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/include/llvm/Transforms/Utils/
H A DSSAUpdaterImpl.h63 SmallVectorImpl<PhiT*> *Ins) :
64 Updater(U), AvailableVals(A), InsertedPHIs(Ins) { }
62 SSAUpdaterImpl(UpdaterT *U, AvailableValsTy *A, SmallVectorImpl<PhiT*> *Ins) argument
/external/llvm/lib/Target/PTX/
H A DPTXISelLowering.cpp194 const SmallVectorImpl<ISD::InputArg> &Ins,
222 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
223 assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
226 unsigned ParamSize = Ins[i].VT.getStoreSizeInBits();
231 SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
237 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
238 EVT RegVT = Ins[i].VT;
350 const SmallVectorImpl<ISD::InputArg> &Ins,
362 // The layout of the ops will be [Chain, #Ins, Ins, Calle
191 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
345 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/Blackfin/
H A DBlackfinISelLowering.cpp167 &Ins,
179 CCInfo.AnalyzeFormalArguments(Ins, CC_Blackfin);
287 const SmallVectorImpl<ISD::InputArg> &Ins,
386 RVInfo.AnalyzeCallResult(Ins, RetCC_Blackfin);
164 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
282 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp239 &Ins,
250 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
260 const SmallVectorImpl<ISD::InputArg> &Ins,
272 Outs, OutVals, Ins, dl, DAG, InVals);
285 &Ins,
299 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
379 const SmallVectorImpl<ISD::InputArg> &Ins,
502 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
513 &Ins,
522 CCInfo.AnalyzeCallResult(Ins, RetCC_System
235 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
255 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
281 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
373 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
510 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp1022 MachineBasicBlock::iterator Ins = MBB->begin(); local
1024 if (Ins != MBB->end())
1025 DL = Ins->getDebugLoc();
1031 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
H A DARMISelLowering.cpp1104 const SmallVectorImpl<ISD::InputArg> &Ins,
1112 CCInfo.AnalyzeCallResult(Ins,
1221 const SmallVectorImpl<ISD::InputArg> &Ins,
1234 Outs, OutVals, Ins, DAG);
1547 if (!Ins.empty())
1552 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1640 const SmallVectorImpl<ISD::InputArg> &Ins,
1685 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1690 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2486 &Ins,
1102 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1216 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1633 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
2483 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/Alpha/
H A DAlphaISelLowering.cpp234 const SmallVectorImpl<ISD::InputArg> &Ins,
341 Ins, dl, DAG, InVals);
350 const SmallVectorImpl<ISD::InputArg> &Ins,
359 CCInfo.AnalyzeCallResult(Ins, RetCC_Alpha);
393 &Ins,
407 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
409 EVT ObjectVT = Ins[ArgNo].VT;
447 FuncInfo->setVarArgsOffset(Ins.size() * 8);
229 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
348 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
390 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.cpp687 const SmallVectorImpl<ISD::InputArg> &Ins,
824 if (!Ins.empty())
830 Ins, dl, DAG, InVals);
837 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
845 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
867 const SmallVectorImpl<ISD::InputArg> &Ins,
888 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze);
993 // the size of Ins and InVals. This only happens when on varg functions
683 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
836 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
866 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp249 &Ins,
260 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
262 if (Ins.empty())
277 const SmallVectorImpl<ISD::InputArg> &Ins,
289 Outs, OutVals, Ins, dl, DAG, InVals);
305 &Ins,
318 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
448 const SmallVectorImpl<ISD::InputArg> &Ins,
560 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
570 const SmallVectorImpl<ISD::InputArg> &Ins,
245 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
272 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
301 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
442 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
568 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp152 &Ins,
165 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
172 if (i == 0 && Ins[i].Flags.isSRet()) {
354 const SmallVectorImpl<ISD::InputArg> &Ins,
596 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
149 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
349 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp637 std::pair<CompositeMap::iterator, bool> Ins = local
640 if (!Ins.second && Ins.first->second != i1d->first) {
644 << getQualifiedName(Ins.first->second) << " or "
/external/llvm/lib/Target/X86/
H A DX86FastISel.cpp1865 SmallVector<ISD::InputArg, 32> Ins; local
1882 Ins.push_back(MyFlags);
1892 CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86);
H A DX86ISelLowering.cpp1546 const SmallVectorImpl<ISD::InputArg> &Ins,
1555 CCInfo.AnalyzeCallResult(Ins, RetCC_X86);
1564 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) {
1625 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { argument
1626 if (Ins.empty())
1629 return Ins[0].Flags.isSRet();
1674 const SmallVectorImpl<ISD::InputArg> &Ins,
1680 ISD::ArgFlagsTy Flags = Ins[i].Flags;
1715 const SmallVectorImpl<ISD::InputArg> &Ins,
1746 CCInfo.AnalyzeFormalArguments(Ins, CC_X8
1544 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1672 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo *MFI, unsigned i) const argument
1712 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2034 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2582 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp872 const SmallVectorImpl<ISD::InputArg> &Ins,
886 Outs, OutVals, Ins, dl, DAG, InVals);
900 const SmallVectorImpl<ISD::InputArg> &Ins,
1015 Ins, dl, DAG, InVals);
1023 const SmallVectorImpl<ISD::InputArg> &Ins,
1032 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1054 const SmallVectorImpl<ISD::InputArg> &Ins,
1066 Ins, dl, DAG, InVals);
1079 &Ins,
1092 CCInfo.AnalyzeFormalArguments(Ins, CC_XCor
867 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
895 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1021 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1051 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1075 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp1119 &Ins,
1139 CCInfo.AnalyzeFormalArguments(Ins, CCC_SPU);
1142 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1143 EVT ObjectVT = Ins[ArgNo].VT;
1272 const SmallVectorImpl<ISD::InputArg> &Ins,
1435 if (!Ins.empty())
1439 if (Ins.empty())
1446 CCRetInfo.AnalyzeCallResult(Ins, CCC_SPU);
1116 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1267 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp6402 SmallVector<ISD::InputArg, 32> Ins; local
6419 Ins.push_back(MyFlags);
6425 Outs, OutVals, Ins, dl, DAG, InVals);
6432 assert((isTailCall || InVals.size() == Ins.size()) &&
6444 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
6447 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
6537 SmallVector<ISD::InputArg, 16> Ins; local
6555 Ins.push_back(RetArg);
6608 Ins.push_back(MyFlags);
6616 F.isVarArg(), Ins,
[all...]
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1609 &Ins,
1614 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1617 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1627 &Ins,
1677 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1738 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1844 &Ins,
1896 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1898 EVT ObjectVT = Ins[ArgNo].VT;
1900 ISD::ArgFlagsTy Flags = Ins[ArgN
1606 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1623 LowerFormalArguments_SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1840 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2293 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
2705 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2731 FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument
2821 LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2844 LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3052 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]

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