/external/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 33 LiveIntervals &LIS, 39 LiveInterval &LI = LIS.getOrCreateInterval(VReg); 157 void LiveRangeEdit::eraseVirtReg(unsigned Reg, LiveIntervals &LIS) { argument 159 LIS.removeInterval(Reg); 165 LiveIntervals &LIS, 203 LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI); 212 LiveIntervals &LIS, VirtRegMap &VRM, 224 SlotIndex Idx = LIS.getInstructionIndex(MI).getDefIndex(); 249 LiveInterval &LI = LIS.getInterval(Reg); 268 eraseVirtReg(Reg, LIS); 32 createFrom(unsigned OldReg, LiveIntervals &LIS, VirtRegMap &VRM) argument 162 foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead, MachineRegisterInfo &MRI, LiveIntervals &LIS, const TargetInstrInfo &TII) argument 211 eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead, LiveIntervals &LIS, VirtRegMap &VRM, const TargetInstrInfo &TII) argument 318 calculateRegClassAndHint(MachineFunction &MF, LiveIntervals &LIS, const MachineLoopInfo &Loops) argument [all...] |
H A D | RegisterCoalescer.cpp | 87 LiveIntervals *LIS; member in class:__anon6653::RegisterCoalescer 419 if (!LIS->hasInterval(CP.getDstReg())) 423 LIS->getInterval(CP.isFlipped() ? CP.getDstReg() : CP.getSrcReg()); 425 LIS->getInterval(CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg()); 426 SlotIndex CopyIdx = LIS->getInstructionIndex(CopyMI).getDefIndex(); 482 LIS->getInstructionFromIndex(ValLR->end.getPrevSlot()); 496 if (LIS->hasInterval(*AS) && IntA.overlaps(LIS->getInterval(*AS))) { 499 LIS->getInterval(*AS).print(dbgs(), TRI); 526 if (!LIS 995 removeIntervalIfEmpty(LiveInterval &li, LiveIntervals *LIS, const TargetRegisterInfo *TRI) argument [all...] |
H A D | InlineSpiller.cpp | 56 LiveIntervals &LIS; member in class:__anon6621::InlineSpiller 141 LIS(pass.getAnalysis<LiveIntervals>()), 234 if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI)) 284 LiveInterval &SnipLI = LIS.getInterval(SnipReg); 370 SV.SpillMBB = LIS.getMBBFromIndex(SV.SpillVNI->def); 388 DepSV.SpillMBB = LIS.getMBBFromIndex(DepSV.SpillVNI->def); 528 LiveInterval &LI = LIS.getInterval(Reg); 529 LiveInterval &OrigLI = LIS.getInterval(Original); 574 MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); 580 LiveInterval &SrcLI = LIS [all...] |
H A D | LiveDebugVariables.cpp | 129 LiveIntervals &LIS, const TargetInstrInfo &TII); 223 /// @param LIS Live intervals analysis. 228 LiveIntervals &LIS, MachineDominatorTree &MDT, 242 LiveIntervals &LIS); 247 LiveIntervals &LIS, MachineDominatorTree &MDT, 264 LiveIntervals &LIS, const TargetInstrInfo &TRI); 284 LiveIntervals *LIS; member in class:__anon6625::LDVImpl 470 LIS->getMBBStartIdx(MBB) : 471 LIS->getInstructionIndex(llvm::prior(MBBI)).getDefIndex(); 488 LiveIntervals &LIS, MachineDominatorTre 485 extendDef(SlotIndex Idx, unsigned LocNo, LiveInterval *LI, const VNInfo *VNI, SmallVectorImpl<SlotIndex> *Kills, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument 547 addDefsFromCopies(LiveInterval *LI, unsigned LocNo, const SmallVectorImpl<SlotIndex> &Kills, SmallVectorImpl<std::pair<SlotIndex, unsigned> > &NewDefs, MachineRegisterInfo &MRI, LiveIntervals &LIS) argument 620 computeIntervals(MachineRegisterInfo &MRI, LiveIntervals &LIS, MachineDominatorTree &MDT, UserValueScopes &UVS) argument 907 findInsertLocation(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS) argument 933 insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo, LiveIntervals &LIS, const TargetInstrInfo &TII) argument 956 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII) argument [all...] |
H A D | SplitKit.cpp | 47 LIS(lis), 71 LSP.first = LIS.getMBBEndIdx(MBB); 73 LSP.first = LIS.getInstructionIndex(FirstTerm); 84 LSP.second = LIS.getInstructionIndex(I); 92 if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad)) 115 UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex()); 132 const_cast<LiveIntervals&>(LIS) 163 MachineFunction::iterator MFI = LIS.getMBBFromIndex(LVI->start); 168 tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB); 246 MFI = LIS [all...] |
H A D | CalcSpillWeights.cpp | 132 if (writes && isExiting && LIS.isLiveOutOfMBB(li, mbb)) 146 if (hweight > bestPhys && LIS.isAllocatable(hint)) 168 if (li.isZeroLength(LIS.getSlotIndexes())) { 179 if (LIS.isReMaterializable(li, 0, isLoad)) {
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H A D | RegAllocBase.h | 94 LiveIntervals *LIS; 102 RegAllocBase(): UserTag(0), TRI(0), MRI(0), VRM(0), LIS(0) {}
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H A D | LiveRangeEdit.h | 133 LiveInterval &create(LiveIntervals &LIS, VirtRegMap &VRM) { argument 134 return createFrom(getReg(), LIS, VRM); 188 /// to erase it from LIS. 189 void eraseVirtReg(unsigned Reg, LiveIntervals &LIS);
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H A D | RegAllocBasic.cpp | 200 for (LiveIntervals::iterator liItr = LIS->begin(), liEnd = LIS->end(); 235 LIS = &lis; 266 for (LiveIntervals::iterator I = LIS->begin(), E = LIS->end(); I != E; ++I) { 307 LIS->removeInterval(VirtReg->reg); 352 LIS->removeInterval(SplitVirtReg->reg); 432 SlotIndexes *Indexes = LIS->getSlotIndexes(); 577 VRM->rewrite(LIS->getSlotIndexes());
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H A D | SplitKit.h | 45 const LiveIntervals &LIS; member in class:llvm::SplitAnalysis 205 LiveIntervals &LIS; member in class:llvm::SplitEditor
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H A D | RegAllocGreedy.cpp | 360 unassign(LIS->getInterval(VirtReg), PhysReg); 374 LiveInterval &LI = LIS->getInterval(VirtReg); 433 LiveInterval *LI = &LIS->getInterval(Queue.top().second); 1515 if (LIS->intervalIsInOneMBB(VirtReg)) { 1626 SA.reset(new SplitAnalysis(*VRM, *LIS, *Loops)); 1627 SE.reset(new SplitEditor(*SA, *LIS, *VRM, *DomTree)); 1636 LIS->addKillFlags();
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H A D | LiveInterval.cpp | 678 const MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def); 684 LI->getVNInfoAt(LIS.getMBBEndIdx(*PI).getPrevSlot())) 718 SlotIndex Idx = LIS.getInstructionIndex(MI);
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/external/llvm/include/llvm/CodeGen/ |
H A D | CalcSpillWeights.h | 44 LiveIntervals &LIS; member in class:llvm::VirtRegAuxInfo 50 MF(mf), LIS(lis), Loops(loops) {}
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H A D | LiveInterval.h | 560 /// // allocate numComps-1 new LiveIntervals into LIS[1..] 561 /// ConEQ.Distribute(LIS); 565 LiveIntervals &LIS; 574 explicit ConnectedVNInfoEqClasses(LiveIntervals &lis) : LIS(lis) {}
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 377 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 590 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 669 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
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H A D | PPCRegisterInfo.cpp | 292 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 603 BuildMI(MBB, II, dl, TII.get(PPC::LIS), SReg)
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H A D | PPCISelLowering.cpp | 913 // Handle 32-bit sext immediates with LIS + addr mode. 918 // Otherwise, break this down into an LIS + disp. 922 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; 1033 // Otherwise, break this down into an LIS + disp. 1036 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
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/external/srec/config/en.us/dictionary/ |
H A D | c0.6 | [all...] |