/external/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86ATTInstPrinter.cpp | 59 void X86ATTInstPrinter::printSSECC(const MCInst *MI, unsigned Op, argument 61 switch (MI->getOperand(Op).getImm()) { 80 const MCOperand &Op = MI->getOperand(OpNo); local 81 if (Op.isImm()) 83 O << (int)Op.getImm(); 85 assert(Op.isExpr() && "unknown pcrel immediate operand"); 86 O << *Op.getExpr(); 92 const MCOperand &Op = MI->getOperand(OpNo); local 93 if (Op.isReg()) { 94 O << '%' << getRegisterName(Op 108 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
H A D | X86IntelInstPrinter.cpp | 49 void X86IntelInstPrinter::printSSECC(const MCInst *MI, unsigned Op, argument 51 switch (MI->getOperand(Op).getImm()) { 68 const MCOperand &Op = MI->getOperand(OpNo); local 69 if (Op.isImm()) 70 O << Op.getImm(); 72 assert(Op.isExpr() && "unknown pcrel immediate operand"); 73 O << *Op.getExpr(); 84 const MCOperand &Op = MI->getOperand(OpNo); local 85 if (Op.isReg()) { 86 PrintRegName(O, getRegisterName(Op 95 printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCWin64EH.h | 36 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg) argument 37 : Operation(Op), Label(L), Offset(0), Register(Reg) { 38 assert(Op == Win64EH::UOP_PushNonVol); 43 MCWin64EHInstruction(OpType Op, MCSymbol *L, unsigned Reg, unsigned Off) argument 44 : Operation(Op), Label(L), Offset(Off), Register(Reg) { 45 assert(Op == Win64EH::UOP_SetFPReg || 46 Op == Win64EH::UOP_SaveNonVol || 47 Op == Win64EH::UOP_SaveNonVolBig || 48 Op == Win64EH::UOP_SaveXMM128 || 49 Op 51 MCWin64EHInstruction(OpType Op, MCSymbol *L, bool Code) argument [all...] |
H A D | MCInst.h | 98 MCOperand Op; local 99 Op.Kind = kRegister; 100 Op.RegVal = Reg; 101 return Op; 104 MCOperand Op; local 105 Op.Kind = kImmediate; 106 Op.ImmVal = Val; 107 return Op; 110 MCOperand Op; local 111 Op 116 MCOperand Op; local 136 setOpcode(unsigned Op) argument 144 addOperand(const MCOperand &Op) argument 154 insert(iterator I, const MCOperand &Op) argument [all...] |
/external/llvm/lib/Target/MSP430/InstPrinter/ |
H A D | MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo); local 37 if (Op.isImm()) 38 O << Op.getImm(); 40 assert(Op.isExpr() && "unknown pcrel immediate operand"); 41 O << *Op.getExpr(); 48 const MCOperand &Op = MI->getOperand(OpNo); local 49 if (Op.isReg()) { 50 O << getRegisterName(Op.getReg()); 51 } else if (Op.isImm()) { 52 O << '#' << Op [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeVectorOps.cpp | 54 SDValue LegalizeOp(SDValue Op); 56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 58 SDValue UnrollVSETCC(SDValue Op); 63 SDValue ExpandUINT_TO_FLOAT(SDValue Op); 66 SDValue ExpandVSELECT(SDValue Op); 67 SDValue ExpandLoad(SDValue Op); 68 SDValue ExpandStore(SDValue Op); 69 SDValue ExpandFNEG(SDValue Op); 73 SDValue PromoteVectorOp(SDValue Op); 106 SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValu argument 113 LegalizeOp(SDValue Op) argument 271 PromoteVectorOp(SDValue Op) argument 295 ExpandLoad(SDValue Op) argument 334 ExpandStore(SDValue Op) argument 385 ExpandVSELECT(SDValue Op) argument 419 ExpandUINT_TO_FLOAT(SDValue Op) argument 459 ExpandFNEG(SDValue Op) argument 468 UnrollVSETCC(SDValue Op) argument [all...] |
H A D | InstrEmitter.cpp | 72 SDValue Op(Node, ResNo); 74 VRBaseMap.erase(Op); 75 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; 107 SDValue Op = User->getOperand(i); local 108 if (Op.getNode() != Node || Op.getResNo() != ResNo) 110 EVT VT = Node->getValueType(Op.getResNo()); 161 SDValue Op(Node, ResNo); 163 VRBaseMap.erase(Op); 164 bool isNew = VRBaseMap.insert(std::make_pair(Op, VRBas 246 getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap) argument 273 AddRegisterOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, const MCInstrDesc *II, DenseMap<SDValue, unsigned> &VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineOperand.h | 472 MachineOperand Op(MachineOperand::MO_Immediate); 473 Op.setImm(Val); 474 return Op; 478 MachineOperand Op(MachineOperand::MO_CImmediate); 479 Op.Contents.CI = CI; 480 return Op; 484 MachineOperand Op(MachineOperand::MO_FPImmediate); 485 Op.Contents.CFP = CFP; 486 return Op; 495 MachineOperand Op(MachineOperan [all...] |
H A D | MachineRegisterInfo.h | 356 MachineOperand *Op; member in class:llvm::MachineRegisterInfo::defusechain_iterator 357 explicit defusechain_iterator(MachineOperand *op) : Op(op) { 374 defusechain_iterator(const defusechain_iterator &I) : Op(I.Op) {} 375 defusechain_iterator() : Op(0) {} 378 return Op == x.Op; 385 bool atEnd() const { return Op == 0; } 389 assert(Op && "Cannot increment end iterator!"); 390 Op [all...] |
/external/llvm/lib/Target/MBlaze/InstPrinter/ |
H A D | MBlazeInstPrinter.cpp | 37 const MCOperand &Op = MI->getOperand(OpNo); local 38 if (Op.isReg()) { 39 O << getRegisterName(Op.getReg()); 40 } else if (Op.isImm()) { 41 O << (int32_t)Op.getImm(); 43 assert(Op.isExpr() && "unknown operand kind in printOperand"); 44 O << *Op.getExpr();
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/external/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 222 MBlazeOperand *Op = new MBlazeOperand(Token); local 223 Op->Tok.Data = Str.data(); 224 Op->Tok.Length = Str.size(); 225 Op->StartLoc = S; 226 Op->EndLoc = S; 227 return Op; 231 MBlazeOperand *Op = new MBlazeOperand(Register); local 232 Op->Reg.RegNum = RegNum; 233 Op->StartLoc = S; 234 Op 239 MBlazeOperand *Op = new MBlazeOperand(Immediate); local 247 MBlazeOperand *Op = new MBlazeOperand(Fsl); local 256 MBlazeOperand *Op = new MBlazeOperand(Memory); local 267 MBlazeOperand *Op = new MBlazeOperand(Memory); local 375 MBlazeOperand *Op; local 458 MBlazeOperand *Op; local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 551 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 572 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const; 589 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 598 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 621 virtual void LowerAsmOperandForConstraint(SDValue Op, 710 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 781 std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 786 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 787 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const; 788 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDA [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 104 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 128 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 129 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 130 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 131 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 132 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 133 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 134 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 135 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 136 SDValue LowerVASTART(SDValue Op, SelectionDA [all...] |
/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | DivZeroChecker.cpp | 34 BinaryOperator::Opcode Op = B->getOpcode(); local 35 if (Op != BO_Div && 36 Op != BO_Rem && 37 Op != BO_DivAssign && 38 Op != BO_RemAssign)
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/external/clang/lib/CodeGen/ |
H A D | CGExprComplex.cpp | 142 ComplexPairTy EmitCast(CastExpr::CastKind CK, Expr *Op, QualType DestTy); 219 ComplexPairTy EmitBinAdd(const BinOpInfo &Op); 220 ComplexPairTy EmitBinSub(const BinOpInfo &Op); 221 ComplexPairTy EmitBinMul(const BinOpInfo &Op); 222 ComplexPairTy EmitBinDiv(const BinOpInfo &Op); 360 ComplexPairTy ComplexExprEmitter::EmitCast(CastExpr::CastKind CK, Expr *Op, argument 366 LValue LV = CGF.EmitLValue(Op); 374 return Visit(Op); 377 llvm::Value *V = CGF.EmitLValue(Op).getAddress(); 425 llvm::Value *Elt = CGF.EmitScalarExpr(Op); 448 ComplexPairTy Op = Visit(E->getSubExpr()); local 465 ComplexPairTy Op = Visit(E->getSubExpr()); local 475 EmitBinAdd(const BinOpInfo &Op) argument 488 EmitBinSub(const BinOpInfo &Op) argument 501 EmitBinMul(const BinOpInfo &Op) argument 525 EmitBinDiv(const BinOpInfo &Op) argument [all...] |
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 87 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 135 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const; 136 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const; 137 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 138 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 139 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 140 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 141 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 142 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 143 SDValue LowerVAARG(SDValue Op, SelectionDA [all...] |
/external/llvm/lib/Target/PTX/InstPrinter/ |
H A D | PTXInstPrinter.cpp | 114 const MCOperand &Op = MI->getOperand(OpNo); local 115 if (Op.isImm()) { 116 O << Op.getImm(); 117 } else if (Op.isFPImm()) { 118 double Imm = Op.getFPImm(); 129 assert(Op.isExpr() && "unknown operand kind in printOperand"); 130 const MCExpr *Expr = Op.getExpr(); 135 O << *Op.getExpr(); 152 const MCOperand &Op = MI->getOperand(OpNo); local 153 assert (Op [all...] |
/external/skia/include/core/ |
H A D | SkClipStack.h | 27 SkRegion::Op op = SkRegion::kIntersect_Op) { 32 void clipDevRect(const SkRect&, SkRegion::Op = SkRegion::kIntersect_Op); 33 void clipDevPath(const SkPath&, SkRegion::Op = SkRegion::kIntersect_Op); 49 SkRegion::Op fOp;
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/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 80 const MCOperand &Op = MI->getOperand(OpNo); local 81 if (Op.isReg()) { 82 printRegName(O, Op.getReg()); 86 if (Op.isImm()) { 87 O << Op.getImm(); 91 assert(Op.isExpr() && "unknown operand kind in printOperand"); 92 O << *Op.getExpr();
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 285 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 295 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 330 virtual void LowerAsmOperandForConstraint(SDValue Op, 386 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 387 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 388 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 389 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 390 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 391 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 392 SDValue LowerSETCC(SDValue Op, SelectionDA [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 242 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 300 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 305 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 330 virtual void LowerAsmOperandForConstraint(SDValue Op, 403 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 404 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 405 SDValue LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG) const; 406 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 408 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 409 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDA [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenInstruction.h | 45 static ConstraintInfo getTied(unsigned Op) { argument 48 I.OtherTiedOperand = Op; 168 std::pair<unsigned,unsigned> ParseOperandName(const std::string &Op, 173 unsigned getFlattenedOperandNumber(std::pair<unsigned,unsigned> Op) const { 174 return OperandList[Op.first].MIOperandNo + Op.second; 179 std::pair<unsigned,unsigned> getSubOperandNumber(unsigned Op) const { 182 if (OperandList[i].MIOperandNo+OperandList[i].MINumOperands > Op) 183 return std::make_pair(i, Op-OperandList[i].MIOperandNo); 191 std::pair<unsigned,unsigned> Op local [all...] |
/external/llvm/utils/PerfectShuffle/ |
H A D | PerfectShuffle.cpp | 89 Operator *Op; // The Operation used to generate this value. member in struct:ShuffleVal 147 static const char *getZeroCostOpName(unsigned short Op) { argument 148 if (ShufTab[Op].Arg0 == 0x0123) 150 else if (ShufTab[Op].Arg0 == 0x4567) 162 std::cerr << " = " << ShufTab[ThisOp].Op->getName() << "("; 176 if (!ShufTab[Vals[ValNo]].Op->isOnlyLHSOperator()) { 222 ShufTab[0x0123].Op = 0; 225 ShufTab[0x4567].Op = 0; 304 Operator *Op = TheOperators[opnum]; 307 unsigned ResultMask = Op [all...] |
/external/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.cpp | 201 const MCOperand &Op = MI->getOperand(OpNo); local 202 if (Op.isReg()) { 203 unsigned Reg = Op.getReg(); 205 } else if (Op.isImm()) { 206 O << '#' << Op.getImm(); 208 assert(Op.isExpr() && "unknown operand kind in printOperand"); 211 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr()); 219 O << *Op.getExpr(); 278 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, argument 280 const MCOperand &MO1 = MI->getOperand(Op); 306 printAM2PostIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O) argument 331 printAddrModeTBB(const MCInst *MI, unsigned Op, raw_ostream &O) argument 339 printAddrModeTBH(const MCInst *MI, unsigned Op, raw_ostream &O) argument 347 printAddrMode2Operand(const MCInst *MI, unsigned Op, raw_ostream &O) argument 393 printAM3PostIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O) argument 413 printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op, raw_ostream &O) argument 434 printAddrMode3Operand(const MCInst *MI, unsigned Op, raw_ostream &O) argument 509 unsigned Op = ARM_AM::getAM5Op(MO2.getImm()); local 606 const MCOperand &Op = MI->getOperand(OpNum); local 615 const MCOperand &Op = MI->getOperand(OpNum); local 621 const MCOperand &Op = MI->getOperand(OpNum); local 633 const MCOperand &Op = MI->getOperand(OpNum); local 759 printThumbAddrModeRROperand(const MCInst *MI, unsigned Op, raw_ostream &O) argument 775 printThumbAddrModeImm5SOperand(const MCInst *MI, unsigned Op, raw_ostream &O, unsigned Scale) argument 793 printThumbAddrModeImm5S1Operand(const MCInst *MI, unsigned Op, raw_ostream &O) argument 799 printThumbAddrModeImm5S2Operand(const MCInst *MI, unsigned Op, raw_ostream &O) argument 805 printThumbAddrModeImm5S4Operand(const MCInst *MI, unsigned Op, raw_ostream &O) argument 811 printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op, raw_ostream &O) argument [all...] |
/external/llvm/include/llvm/Bitcode/ |
H A D | BitstreamWriter.h | 262 void EmitAbbreviatedLiteral(const BitCodeAbbrevOp &Op, uintty V) { argument 263 assert(Op.isLiteral() && "Not a literal"); 266 assert(V == Op.getLiteralValue() && 273 void EmitAbbreviatedField(const BitCodeAbbrevOp &Op, uintty V) { argument 274 assert(!Op.isLiteral() && "Literals should use EmitAbbreviatedLiteral!"); 277 switch (Op.getEncoding()) { 280 if (Op.getEncodingData()) 281 Emit((unsigned)V, (unsigned)Op.getEncodingData()); 284 if (Op.getEncodingData()) 285 EmitVBR64(V, (unsigned)Op 311 const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i); local 461 const BitCodeAbbrevOp &Op = Abbv->getOperandInfo(i); local [all...] |