Searched refs:Pred (Results 76 - 100 of 130) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp220 SUnit &Pred = *I->getSUnit(); local
221 if (!Pred.isScheduled) {
224 if (OnlyAvailablePred && OnlyAvailablePred != &Pred)
226 OnlyAvailablePred = &Pred;
H A DScheduleDAGRRList.cpp1017 const SDep &Pred = ChainPreds[i]; local
1018 RemovePred(SU, Pred);
1020 AddPred(LoadSU, Pred);
1023 const SDep &Pred = LoadPreds[i]; local
1024 RemovePred(SU, Pred);
1026 AddPred(LoadSU, Pred);
1029 const SDep &Pred = NodePreds[i]; local
1030 RemovePred(SU, Pred);
1031 AddPred(NewSU, Pred);
/external/llvm/lib/CodeGen/
H A DTargetInstrInfoImpl.cpp166 const SmallVectorImpl<MachineOperand> &Pred) const {
180 MO.setReg(Pred[j].getReg());
183 MO.setImm(Pred[j].getImm());
186 MO.setMBB(Pred[j].getMBB());
H A DMachineSSAUpdater.cpp323 MachineBasicBlock *Pred) {
325 PHI->addOperand(MachineOperand::CreateMBB(Pred));
322 AddPHIOperand(MachineInstr *PHI, unsigned Val, MachineBasicBlock *Pred) argument
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h167 ARMCC::CondCodes Pred = ARMCC::AL,
H A DARMBaseInstrInfo.cpp157 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); local
171 .addImm(Pred).addReg(0).addReg(0);
178 .addImm(Pred).addReg(0).addReg(0);
183 .addImm(Pred).addReg(0).addReg(0);
194 .addImm(Pred).addReg(0).addReg(0);
199 .addImm(Pred).addReg(0).addReg(0);
209 .addReg(WBReg).addImm(0).addImm(Pred);
213 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
220 .addReg(BaseReg).addImm(0).addImm(Pred);
224 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
1577 emitARMRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, ARMCC::CondCodes Pred, unsigned PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument
[all...]
H A DARMConstantIslandPass.cpp1075 MachineBasicBlock *Pred = *MBB->pred_begin(); local
1076 MachineInstr *PredMI = &Pred->back();
1819 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); local
1820 if (Pred == ARMCC::EQ)
1822 else if (Pred == ARMCC::NE)
1837 Pred = getInstrPredicate(CmpMI, PredReg);
1838 if (Pred == ARMCC::AL &&
H A DARMISelDAGToDAG.cpp1649 SDValue Pred = getAL(CurDAG); local
1672 Ops.push_back(Pred);
1686 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1702 Ops.push_back(Pred);
1775 SDValue Pred = getAL(CurDAG); local
1823 Ops.push_back(Pred);
1849 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1867 Ops.push_back(Pred);
1939 SDValue Pred = getAL(CurDAG); local
1970 Ops.push_back(Pred);
2035 SDValue Pred = getAL(CurDAG); local
2598 SDValue Pred = getAL(CurDAG); local
2835 SDValue Pred = getAL(CurDAG); local
2855 SDValue Pred = getAL(CurDAG); local
2874 SDValue Pred = getAL(CurDAG); local
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h127 std::vector<MachineOperand> &Pred) const;
/external/llvm/lib/Transforms/Scalar/
H A DGVN.cpp115 uint32_t lookup_or_add_cmp(unsigned Opcode, CmpInst::Predicate Pred,
1572 BasicBlock *Pred = *PI; local
1573 if (IsValueFullyAvailableInBlock(Pred, FullyAvailableBlocks)) {
1576 PredLoads[Pred] = 0;
1578 if (Pred->getTerminator()->getNumSuccessors() != 1) {
1579 if (isa<IndirectBrInst>(Pred->getTerminator())) {
1581 << Pred->getName() << "': " << *LI << '\n');
1588 << Pred->getName() << "': " << *LI << '\n');
1592 unsigned SuccNum = GetSuccessorNumber(Pred, LoadBB);
1593 NeedToSplit.push_back(std::make_pair(Pred
2105 BasicBlock *Pred = Dst->getSinglePredecessor(); local
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H A DCodeGenPrepare.cpp288 BasicBlock *Pred = DestBBPN->getIncomingBlock(i); local
289 if (BBPreds.count(Pred)) { // Common predecessor?
292 const Value *V1 = PN->getIncomingValueForBlock(Pred);
298 V2 = V2PN->getIncomingValueForBlock(Pred);
H A DJumpThreading.cpp1084 BasicBlock *Pred = PredValues[i].second; local
1085 if (!SeenPreds.insert(Pred))
1090 if (isa<IndirectBrInst>(Pred->getTerminator()))
1114 PredToDestList.push_back(std::make_pair(Pred, DestBB));
1135 BasicBlock *Pred = PredToDestList[i].first; local
1140 TerminatorInst *PredTI = Pred->getTerminator();
1143 PredsToFactor.push_back(Pred);
H A DScalarReplAggregates.cpp1089 BasicBlock *Pred = PN->getIncomingBlock(i); local
1094 if (Pred->getTerminator()->mayHaveSideEffects())
1099 if (Pred->getTerminator() == InVal)
1103 if (Pred->getTerminator()->getNumSuccessors() == 1)
1109 isSafeToLoadUnconditionally(InVal, Pred->getTerminator(), MaxAlign, TD))
1270 BasicBlock *Pred = PN->getIncomingBlock(i); local
1271 LoadInst *&Load = InsertedLoads[Pred];
1274 PN->getName() + "." + Pred->getName(),
1275 Pred->getTerminator());
1280 NewPN->addIncoming(Load, Pred);
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/external/llvm/lib/Analysis/
H A DMemoryDependenceAnalysis.cpp1154 BasicBlock *Pred = *PI; local
1155 PredList.push_back(std::make_pair(Pred, Pointer));
1160 PredPointer.PHITranslateValue(BB, Pred, 0);
1170 InsertRes = Visited.insert(std::make_pair(Pred, PredPtrVal));
1200 BasicBlock *Pred = PredList[i].first; local
1223 isLoad, Pred,
1226 NonLocalDepResult Entry(Pred, MemDepResult::getUnknown(), PredPtrVal);
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineAndOrXor.cpp111 CmpInst::Predicate Pred; local
114 case 0: Pred = isordered ? FCmpInst::FCMP_ORD : FCmpInst::FCMP_UNO; break;
115 case 1: Pred = isordered ? FCmpInst::FCMP_OGT : FCmpInst::FCMP_UGT; break;
116 case 2: Pred = isordered ? FCmpInst::FCMP_OEQ : FCmpInst::FCMP_UEQ; break;
117 case 3: Pred = isordered ? FCmpInst::FCMP_OGE : FCmpInst::FCMP_UGE; break;
118 case 4: Pred = isordered ? FCmpInst::FCMP_OLT : FCmpInst::FCMP_ULT; break;
119 case 5: Pred = isordered ? FCmpInst::FCMP_ONE : FCmpInst::FCMP_UNE; break;
120 case 6: Pred = isordered ? FCmpInst::FCMP_OLE : FCmpInst::FCMP_ULE; break;
123 Pred = FCmpInst::FCMP_ORD; break;
125 return Builder->CreateFCmp(Pred, LH
501 decomposeBitTestICmp(const ICmpInst *I, ICmpInst::Predicate &Pred, Value *&X, Value *&Y, Value *&Z) argument
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H A DInstCombineCasts.cpp886 ICmpInst::Predicate Pred = ICI->getPredicate(); local
891 if ((Pred == ICmpInst::ICMP_SLT && Op1C->isZero()) ||
892 (Pred == ICmpInst::ICMP_SGT && Op1C->isAllOnesValue())) {
900 if (Pred == ICmpInst::ICMP_SGT)
920 Value *V = Pred == ICmpInst::ICMP_NE ?
926 if (!Op1C->isZero() == (Pred == ICmpInst::ICMP_NE)) {
963 if (Pred == ICmpInst::ICMP_SLT && match(Op1, m_Zero()) &&
/external/clang/include/clang/StaticAnalyzer/Core/
H A DCheckerManager.h50 virtual void expandGraph(ExplodedNodeSet &Dst, ExplodedNode *Pred) = 0;
256 ExplodedNodeSet &Dst, ExplodedNode *Pred,
388 ExplodedNode *Pred,
H A DChecker.h343 ExplodedNode *Pred,
345 return ((const CHECKER *)checker)->inlineCall(CE, Eng, Pred, Dst);
341 _inlineCall(void *checker, const CallExpr *CE, ExprEngine &Eng, ExplodedNode *Pred, ExplodedNodeSet &Dst) argument
/external/llvm/lib/Target/PTX/
H A DPTXAsmPrinter.cpp58 case PTXRegisterType::Pred:
190 numRegs = MFI->countRegisters(PTXRegisterType::Pred, PTXRegisterSpace::Reg);
/external/llvm/lib/Transforms/Utils/
H A DSSAUpdater.cpp308 static void AddPHIOperand(PHINode *PHI, Value *Val, BasicBlock *Pred) { argument
309 PHI->addIncoming(Val, Pred);
H A DSimplifyCFG.cpp65 BasicBlock *Pred,
552 BasicBlock *Pred,
554 Value *PredVal = isValueEqualityComparison(Pred->getTerminator());
561 // Find out information about when control will move from Pred to TI's block.
563 BasicBlock *PredDef = GetValueEqualityComparisonCases(Pred->getTerminator(),
572 // If TI's block is the default block from Pred's comparison, potentially
592 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator()
605 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator()
656 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator()
697 BasicBlock *Pred local
551 SimplifyEqualityComparisonWithOnlyPredecessor(TerminatorInst *TI, BasicBlock *Pred, IRBuilder<> &Builder) argument
2071 BasicBlock *Pred = BB->getSinglePredecessor(); local
2324 BasicBlock *Pred = UncondBranchPreds.pop_back_val(); local
2326 << "INTO UNCOND BRANCH PRED: " << *Pred); local
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/external/llvm/utils/TableGen/
H A DDAGISelMatcher.cpp89 : Matcher(CheckPredicate), Pred(pred.getOrigPatFragRecord()) {}
92 return TreePredicateFn(Pred);
/external/llvm/lib/Target/PTX/InstPrinter/
H A DPTXInstPrinter.cpp55 case PTXRegisterType::Pred:
/external/llvm/bindings/ocaml/llvm/
H A Dllvm_ocaml.c695 CAMLprim LLVMValueRef llvm_const_icmp(value Pred, argument
698 return LLVMConstICmp(Int_val(Pred) + LLVMIntEQ, LHSConstant, RHSConstant);
702 CAMLprim LLVMValueRef llvm_const_fcmp(value Pred, argument
705 return LLVMConstFCmp(Int_val(Pred), LHSConstant, RHSConstant);
1846 CAMLprim LLVMValueRef llvm_build_icmp(value Pred, argument
1849 return LLVMBuildICmp(Builder_val(B), Int_val(Pred) + LLVMIntEQ, LHS, RHS,
1854 CAMLprim LLVMValueRef llvm_build_fcmp(value Pred, argument
1857 return LLVMBuildFCmp(Builder_val(B), Int_val(Pred), LHS, RHS,
/external/llvm/lib/Support/
H A DConstantRange.cpp51 ConstantRange ConstantRange::makeICmpRegion(unsigned Pred, argument
57 switch (Pred) {

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