Searched refs:SubReg1 (Results 1 - 2 of 2) sorted by relevance
| /external/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfoImpl.cpp | 82 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); local
97 SubReg0 = SubReg1;
108 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1);
112 .addReg(Reg1, getKillRegState(Reg1IsKill), SubReg1);
121 MI->getOperand(Idx2).setSubReg(SubReg1);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 1458 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); local
1459 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1469 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); local
1470 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1480 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); local
1481 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1493 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32); local
1496 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1508 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32); local
1511 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1523 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32); local
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