| 43600e95ec3690b37d458a6d3d56941ad84cddcb |
|
13-Aug-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the TII::scheduleTwoAddrSource() hook.
It never does anything when running 'make check', and it get's in the
way of updating live intervals in 2-addr.
The hook was originally added to help form IT blocks in Thumb2 code
before register allocation, but the pass ordering has changed since
then, and we run if-conversion after register allocation now.
When the MI scheduler is enabled, there will be no less than two
schedulers between 2-addr and Thumb2ITBlockPass, so this hook is
unlikely to help anything.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 420761a0f193e87d08ee1c51b26bba23ab4bac7f |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 4e02f23de24375294005f88b5254a3775d39fcb2 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| c89c744b69cecac576317a98322fd295e36e9886 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove unnecessary llvm:: qualifications
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| c1f6f42049696e7357fb4837e1b25dabbaed3fe6 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes to match coding standards. Fix an issue or two exposed by that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| c01810eeb7227010f73cb39e3c4fa0197a3c4ef0 |
|
29-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM implement TargetInstrInfo::getNoopForMachoTarget()
Without this hook, functions w/ a completely empty body (including no
epilogue) will cause an MCEmitter assertion failure.
For example,
define internal fastcc void @empty_function() {
unreachable
}
rdar://10947471
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 2420b558de5d291d8503c1339004e5b5bf99a48a |
|
17-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle regmask operands in ARMInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 978e0dfe46e481bfb1281e683aa308329e879e95 |
|
15-Nov-2011 |
Jay Foad <jay.foad@gmail.com> |
Make use of MachinePointerInfo::getFixedStack. This removes all mention
of PseudoSourceValue from lib/Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 5b81584f7403ffdb9cc6babaaeb0411c080e0f81 |
|
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.
Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 796d6b7602f0279b52ff5c105fb73fbdf444f030 |
|
11-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Handle new register classes in Thumb2 mode. Should fix the ARM buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| ee04a6d3a40c3017124e3fd89a0db473a2824498 |
|
21-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Refact ARM Thumb1 tMOVr instruction family.
Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 63b46faeb8acae9b7e5f865b7417dc00b9b9dad3 |
|
01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb1 register to register MOV instruction is predicable.
Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134197 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| dafc17e2c2a13697f7f80f5965104290e2912464 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Kill dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| f6fd90910a552ad9883f031350ae517e26dfdb44 |
|
30-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant Thumb2 ADD/SUB SP instruction definitions.
Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 22fee2dff4c43b551aefa44a96ca74fcade6bfac |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e837dead3c8dc3445ef6a0e2322179c57e264a13 |
|
28-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 57caad7a33ff145b71545f10dcfbbf2fd0f595d3 |
|
05-Mar-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Preliminary support for ARM frame save directives emission via MI flags.
This is just very first approximation how the stuff should be done
(e.g. ARM-only for now). More to follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 0a921698b6d6f8a40df3893a72c7e6ced1c919a0 |
|
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Guard against de-referencing MBB.end().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 557b297f35395a6104a77ed6a798f10c2b46bfbe |
|
22-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Skipping over debugvalue instructions to determine whether the split spot is in a IT block. rdar://9030770
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 48575f6ea7d5cd21ab29ca370f58fcf9ca31400b |
|
05-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.
Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.
A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.
Work in progress, only A+B are enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 8239daf7c83a65a189c352cce3191cdc3bbfe151 |
|
03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Two sets of changes. Sorry they are intermingled.
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e3cc84a43d6a4bb6c50f58f3dd8e60e28787509e |
|
02-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Thread the determination of branch prediction hit rates back through the if-conversion heuristic APIs. For now,
stick with a constant estimate of 90% (branch predictors are good!), but we might find that we want to provide
more nuanced estimates in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115364 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| aa9f0a57d03b1eef5a58c48b05f6657d2a5a0d0a |
|
01-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide an option to restore old-style if-conversion heuristics for Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b20b85168c0e9819e6545f08281e9b83c82108f0 |
|
28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 59db5496f4fc2ef6111569e542f8b65480ef14c1 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
convert targets to the new MF.getMachineMemOperand interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
|
10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 6ccfc507dc1f7ad8c8964193a2407264ca644f0d |
|
30-Jul-2010 |
Jim Grosbach <grosbach@apple.com> |
Many Thumb2 instructions can reference the full ARM register set (i.e.,
have 4 bits per register in the operand encoding), but have undefined
behavior when the operand value is 13 or 15 (SP and PC, respectively).
The trivial coalescer in linear scan sometimes will merge a copy from
SP into a subsequent instruction which uses the copy, and if that
instruction cannot legally reference SP, we get bad code such as:
mls r0,r9,r0,sp
instead of:
mov r2, sp
mls r0, r9, r0, r2
This patch adds a new register class for use by Thumb2 that excludes
the problematic registers (SP and PC) and is used instead of GPR
for those operands which cannot legally reference PC or SP. The
trivial coalescer explicitly requires that the register class
of the destination for the COPY instruction contain the source
register for the COPY to be considered for coalescing. This prevents
errant instructions like that above.
PR7499
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| ac2736670034e8942939b9fccf8e4618a0bda908 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 1ab38469dfa8050724a8443d7b7ef2885e11e1db |
|
29-Jun-2010 |
Bob Wilson <bob.wilson@apple.com> |
The t2MOVi16 and t2MOVTi16 instructions do not set CPSR. Trying to add
a CPSR operand to them causes an assertion failure, so apparently these
instructions haven't been getting a lot of use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107147 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| c170f66742f84367e9922e5dd1953d696788a8be |
|
29-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-cvt options to something that actually as useable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 13151432edace19ee867a93b5c14573df4f75d24 |
|
26-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change if-conversion block size limit checks to add some flexibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 4d54e5b2dd4a3d3bed38ff9c7aa57fc66adb5855 |
|
22-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Tail merging pass shall not break up IT blocks. rdar://8115404
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 86050dc8cc0aaea8c9dfeb89de02cafbd7f48d92 |
|
19-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
scheduler. If-converter now runs branch folding / tail merging first to
maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
change the instruction ordering in the IT block (since IT mask has been
finalized). It also ensures no other instructions can be scheduled between
instructions in the IT block.
This is not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 6470a116f17b70aba0c2e7ee751551a5ac9797f6 |
|
16-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 68fc2daf8fa446be04d2ed2b3cbb1b00c382458f |
|
09-Jun-2010 |
Evan Cheng <evan.cheng@apple.com> |
Allow target to place 2-address pass inserted copies in better spots. Thumb2 will use this to try to avoid breaking up IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 18f30e6f5e80787808fe1455742452a5210afe07 |
|
02-Jun-2010 |
Jim Grosbach <grosbach@apple.com> |
Clean up 80 column violations. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 5dfa87ecc6a8b94096869ca0558c5437006d13b3 |
|
27-Apr-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle register-to-register copies within the tGPR class.
Radar 7896289
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 9ab042701528bc104053f93135ef7fd1bbb1153b |
|
27-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not pass
through to the generic version. The generic functions use STR/LDR, but T2
needs the t2STR/t2LDR instead so we get the addressing mode correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99678 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| f5fd499791bd65a31183324dabc5eefc201f9e2e |
|
08-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bit
immediate instructions cannot set the condition codes, so they do not have
the extra cc_out operand. We hit an assertion during tail duplication
because the instruction being duplicated had more operands that expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e6373eb8264ba4804de28d8224e9f7725d3a483c |
|
06-Feb-2010 |
Bob Wilson <bob.wilson@apple.com> |
Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.
Radar 7614112.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 35f0febcb66b5a50a5a750efcbefc95f7fc25c7b |
|
19-Jan-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove predicates when changing an add into an unpredicable mov.
Since the mov is executed unconditionally, make sure that the add didn't have
any predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93909 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
|
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| fdc834046efd427d474e3b899ec69354c05071e0 |
|
08-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 31c24bf5b39cc8391d4cfdbf8cf5163975fdb81e |
|
07-Nov-2009 |
Jim Grosbach <grosbach@apple.com> |
80-column cleanup of file header comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86408 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| bf992817f28bdab09fe1d1349561efb0c89fb0dd |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
t2ldrpci_pic can be used for blockaddress as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86400 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| d457e6e9a5cd975baf4d1f0578382ab8373e6153 |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Refactor code. Fix a potential missing check. Teach isIdentical() about tLDRpci_pic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 78e5c1140adc926e7c004748c1c912bfddd875b4 |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdentical
except it doesn't care if the definitions' virtual registers differ. This is
used by machine LICM and other MI passes to perform CSE.
- Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical.
Since pc relative constantpool entries are always different, this requires it
it check if the values can actually the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b9803a8fa65f043c96612fa9c5aeeee12739db2b |
|
07-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
- Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relative
load of a GV from constantpool and then add pc. It allows the code sequence to
be rematerializable so it would be hoisted by machine licm.
- Add a late pass to break these pseudo instructions into a number of real
instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm
to this pass. This is done before post regalloc scheduling to allow the
scheduler to proper schedule these instructions. It also allow them to be
if-converted and shrunk by later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| f95215f551949d5e5adfbf4753aa833b9009b77a |
|
02-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use NEON reg-reg moves, where profitable. This reduces "domain-cross" stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e3ce8aab0a6de939f8cfa4f8cb2e3a3bf4e1fe21 |
|
01-Nov-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix a couple more places where we are creating ld / st instructions without memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 8d4de5abfa1bcd974554ea14904ebf7af289e84d |
|
28-Oct-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate the
opcode and operand with a tab. Check for these instructions in the usual
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85411 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e4863f47596794df3dd955b6b7064863c50eabe4 |
|
15-Sep-2009 |
Bob Wilson <bob.wilson@apple.com> |
Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs for
VLDM/VSTM instructions, and without this check, the code assumes that an
offset is allowed, as it would be with VLDR/VSTR. The asm printer,
however, silently drops the offset, producing incorrect code. Since the
address register in this case is either the stack or frame pointer, the
spill location ends up conflicting with some other stack slot or with
outgoing arguments on the stack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| cdbb3f5d3311e0f46d22bc8daa211b2fab3541cb |
|
27-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 764ab52dd80310a205c9888bf166d09dab858f90 |
|
11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 09d97354edb65473e61337f543b66855896de134 |
|
10-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e118cb614643c568716ee612366cae4c365a8aa3 |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78398 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 861986401e05e437cb33bfd8320d510b956fe41e |
|
07-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| a8e8984ee4c197634839cf228f5b1d79a77fa4b9 |
|
03-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the i12 variant of load / store opcodes if offset is zero. Now we pass all of multisource as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| d90183d25dcbc0eabde56319fed4e8d6ace2e6eb |
|
02-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
Move the getInlineAsmLength virtual method from TAI to TII, where
the only real caller (GetFunctionSizeInBytes) uses it.
The custom ARM implementation of this is basically reimplementing
an assembler poorly for negligible gain. It should be removed
IMNSHO, but I'll leave that to ARMish folks to decide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 5657c01949dca6c012ac60d242d1a8d2ffdf5603 |
|
29-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| d9453784fbcbbf052a32752d00e3b7d0004fda55 |
|
29-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Thumb-2: fix typo that caused incorrect stack elimination for VFP operations and very large stack frames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77401 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 6495f63945e8dbde81f03a1dc2ab421993b9a495 |
|
28-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
- More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| e0f21bd47f3fed91124e3d8187e1bf8a66c6aef3 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
More DCE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| fc17fb0aeed584b8560461ab2843d0676a243f29 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of more dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 5ca53a7ad821613d324e4189ddbb0d468a326146 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of some more getOpcode calls.
This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 5732ca084aaa0cd26149e50dd4b487efff37fe41 |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 08b93c6a70ae59af375f205cfcffeaa3517577ab |
|
27-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Use the right instructions to copy between GPR and the more strictive tGPR classes. t2MOV does not match the RC requirements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| c6b54d5a33ca5341da8d6ccc3140a5b67475e7f4 |
|
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Get rid of a couple of unnecessary getOpcode calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77035 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 66ac53165e17b7c76b8c69e57bde623d44ec492e |
|
25-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change Thumb2 jumptable codegen to one that uses two level jumps:
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 23606e35ab48ab106ca0fcd29338349d5d77f54a |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b74bb1a7a471a77e793d90de158aa4bbc67fe94d |
|
24-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 5ff58b5c3ab6df332600678798ea5c69c5e943d3 |
|
24-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b53cc014d0f47b898c9daca34566c16dda6c4c1e |
|
23-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b8e9ac834a9c253e3f8f5caa8f229bafba0b4fcf |
|
17-Jul-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit cross regclass register moves for thumb2.
Minor code duplication cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 446c428bf394b7113b0f18cbacb5e87b4efd1e14 |
|
11-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b1beca635fcac095c6227c6518a35e165f8f03bc |
|
10-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
t2LDM_RET does not fall-through.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 |
|
09-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Use common code for both ARM and Thumb-2 instruction and register info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 77521f5232e679aa3de10aaaed2464aa91d7ff55 |
|
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Generalize opcode selection in ARMBaseRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| 334c26473bba3ad8b88341bb0d25d0ac2008bb8d |
|
08-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|
| b50ea5c48f8b1ce259e034ca5c16dc14af1a582c |
|
03-Jul-2009 |
David Goodwin <david_goodwin@apple.com> |
Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
|