| 75dc33a60b65bbbf2253b0b916df1d36a4da4237 |
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18-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Make x86 asm parser to check for xmm vs ymm for index register in gather instructions. Also fix Intel syntax for gather instructions to use 'DWORD PTR' or 'QWORD PTR' to match gas.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160420 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| a28101e61aa3aeed5baf3d5b91d0f8bcb4e9e12a |
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27-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel Syntax: Parse mem operand with seg reg. QWORD PTR FS:[320]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| f2d213745e07e884c1616f2f3d0b78f9e918e5db |
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23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify parsing of memory operand's displacement experssion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 3e08131185d5b3245065eb027900aed56b607970 |
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23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse memory operand with empty base reg, e.g. DWORD PTR [4*RDI]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 7c64fe651ad4581ac66b6407116144442a8a7f03 |
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23-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse segment registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 1aea430b8834f7bed3a14eda5027eac2133d6496 |
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20-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify register parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| b8ba13f0096b560ee618512019ca86969a9fa772 |
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18-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Process instructions after match to select alternative encoding which may be more desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 2f8af1d643cde711b292117e50b30452877432ef |
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17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Fix parser match class to check memory operand size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 6220fea2a877e5cff559ed38e98c59a076ea9825 |
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17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Parse "BYTE PTR [RDX + RCX]"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 9a3d293cf3f72b3c0ed5d4474fc5d4d12fd36be2 |
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17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Do not unncessarily create plus expression for memory operand displacement.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 40bced0306e953c3d0fec19db4c4770b0e3c787e |
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17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Ignore mnemonic aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| d37ad247cc04c2a436e537767ac1aec709901594 |
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17-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Intel syntax: Robustify memory operand parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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| 4a5c0fd70e7a2001b682c8972dab6b0127313c8f |
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13-Jan-2012 |
Devang Patel <dpatel@apple.com> |
Add new test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/intel-syntax.s
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