| ac580fbc5a2b2710f3c87b01ffe4bd3a208e521e |
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24-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 SARX, SHRX, and SHLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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| 9106886843f78e0ad6360bf07bc070643da4068c |
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23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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| 717cdb0df88ddf704f057fb70ed7093836222609 |
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19-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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| ee62e4f6d192ee31d1ad9dd0ba0c41db6663d3c7 |
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16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
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16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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| 17730847d59c919d97f097d46a3fcba1888e5300 |
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16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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| 566f233ba64c0bb2773b5717cb18753c7564f4b7 |
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15-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/X86/x86_64-bmi-encoding.s
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