Cross Reference: /external/llvm/tblgen-rules.mk

Lines Matching refs:td
2 ## Commands for running tblgen to compile a td file
4 define transform-td-to-out
6 	$(call transform-host-td-to-out,$(1)),	\
7 	$(call transform-device-td-to-out,$(1)))
11 ## TableGen: Compile .td files to .inc.
30 $(intermediates)/%GenRegisterNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
31 	$(call transform-td-to-out,register-enums)
36 $(intermediates)/%GenRegisterInfo.h.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
37 	$(call transform-td-to-out,register-desc-header)
42 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
43 	$(call transform-td-to-out,register-desc)
48 $(intermediates)/%GenInstrNames.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
49 	$(call transform-td-to-out,instr-enums)
54 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
55 	$(call transform-td-to-out,instr-desc)
60 $(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
61 	$(call transform-td-to-out,asm-writer)
66 $(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
67 	$(call transform-td-to-out,asm-writer -asmwriternum=1)
72 $(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
73 	$(call transform-td-to-out,asm-matcher)
78 $(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
79 	$(call transform-td-to-out,emitter)
84 $(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
85 	$(call transform-td-to-out,emitter -mc-emitter)
90 $(intermediates)/%GenMCPseudoLowering.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
91 	$(call transform-td-to-out,pseudo-lowering)
96 $(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
97 	$(call transform-td-to-out,dag-isel)
102 $(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
103 	$(call transform-td-to-out,disassembler)
108 $(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
109 	$(call transform-td-to-out,enhanced-disassembly-info)
114 $(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
115 	$(call transform-td-to-out,fast-isel)
120 $(intermediates)/%GenSubtargetInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
121 	$(call transform-td-to-out,subtarget)
126 $(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
127 	$(call transform-td-to-out,callingconv)
132 $(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
133 	$(call transform-td-to-out,tgt_intrinsics)
138 $(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN)
139 	$(call transform-td-to-out,arm-decoder)