/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.cpp | 31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) { argument 32 if (RC == &NVPTX::Float32RegsRegClass) { 35 if (RC == &NVPTX::Float64RegsRegClass) { 38 else if (RC == &NVPTX::Int64RegsRegClass) { 41 else if (RC == &NVPTX::Int32RegsRegClass) { 44 else if (RC == &NVPTX::Int16RegsRegClass) { 48 else if (RC == &NVPTX::Int8RegsRegClass) { 51 else if (RC == &NVPTX::Int1RegsRegClass) { 54 else if (RC == &NVPTX::SpecialRegsRegClass) { 57 else if (RC 93 getNVPTXRegClassStr(TargetRegisterClass const *RC) argument 154 isNVPTXVectorRegClass(TargetRegisterClass const *RC) argument 178 getNVPTXElemClassName(TargetRegisterClass const *RC) argument 202 getNVPTXElemClass(TargetRegisterClass const *RC) argument 226 getNVPTXVectorSize(TargetRegisterClass const *RC) argument [all...] |
H A D | NVPTXRegisterInfo.h | 82 std::string getNVPTXRegClassName (const TargetRegisterClass *RC); 83 std::string getNVPTXRegClassStr (const TargetRegisterClass *RC); 84 bool isNVPTXVectorRegClass (const TargetRegisterClass *RC); 85 std::string getNVPTXElemClassName (const TargetRegisterClass *RC); 86 int getNVPTXVectorSize (const TargetRegisterClass *RC); 87 const TargetRegisterClass *getNVPTXElemClass(const TargetRegisterClass *RC);
|
/external/llvm/include/llvm/CodeGen/ |
H A D | RegisterClassInfo.h | 60 // Compute all information about RC. 61 void compute(const TargetRegisterClass *RC) const; 63 // Return an up-to-date RCInfo for RC. 64 const RCInfo &get(const TargetRegisterClass *RC) const { 65 const RCInfo &RCI = RegClass[RC->getID()]; 67 compute(RC); 79 /// registers in RC in the current function. 80 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { 81 return get(RC).NumRegs; 84 /// getOrder - Returns the preferred allocation order for RC [all...] |
H A D | FastISel.h | 246 const TargetRegisterClass *RC); 252 const TargetRegisterClass *RC, 259 const TargetRegisterClass *RC, 267 const TargetRegisterClass *RC, 276 const TargetRegisterClass *RC, 284 const TargetRegisterClass *RC, 292 const TargetRegisterClass *RC, 300 const TargetRegisterClass *RC, 309 const TargetRegisterClass *RC, 317 const TargetRegisterClass *RC, [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsMachineFunction.cpp | 36 const TargetRegisterClass *RC; local 38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 40 RC = ST.isABI_N64() ? 43 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
|
/external/llvm/lib/CodeGen/ |
H A D | LiveStackAnalysis.cpp | 55 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) { argument 61 S2RCMap.insert(std::make_pair(Slot, RC)); 65 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC); 77 const TargetRegisterClass *RC = getIntervalRegClass(Slot); local 78 if (RC) 79 OS << " [" << RC->getName() << "]\n";
|
H A D | AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); local 45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, 65 ArrayRef<unsigned> O = RCI.getOrder(RC); 72 !RC->contains(Hint) || RCI.isReserved(Hint)))
|
H A D | RegisterClassInfo.cpp | 70 /// compute - Compute the preferred allocation order for RC with reserved 73 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 74 RCInfo &RCI = RegClass[RC->getID()]; 77 unsigned NumRegs = RC->getNumRegs(); 87 ArrayRef<uint16_t> RawOrder = RC->getRawAllocationOrder(*MF); 109 // Check if RC is a proper sub-class. 110 if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC)) 111 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 115 dbgs() << "AllocationOrder(" << RC->getName() << ") = [";
|
H A D | RegisterScavenging.cpp | 233 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const { 234 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 246 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) { argument 248 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); 326 unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC, argument 331 TRI->getAllocatableSet(*I->getParent()->getParent(), RC); 345 BitVector Available = getRegsAvailable(RC); 368 if (!TRI->saveScavengerRegister(*MBB, I, UseMI, RC, SRe [all...] |
/external/llvm/lib/Target/ |
H A D | TargetRegisterInfo.cpp | 73 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const { 74 if (!RC || RC->isAllocatable()) 75 return RC; 77 const unsigned *SubClass = RC->getSubClassMask(); 104 const TargetRegisterClass* RC = *I; local 105 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 106 (!BestRC || BestRC->hasSubClass(RC))) 107 BestRC = RC; 116 getAllocatableSetForRC(const MachineFunction &MF, const TargetRegisterClass *RC, BitVector &R) argument 221 const TargetRegisterClass *RC = local [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 124 bool hasSubClass(const TargetRegisterClass *RC) const { 125 return RC != this && hasSubClassEq(RC); 128 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this 130 bool hasSubClassEq(const TargetRegisterClass *RC) const { 131 unsigned ID = RC->getID(); 137 bool hasSuperClass(const TargetRegisterClass *RC) const { 138 return RC->hasSubClass(this); 141 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this 143 bool hasSuperClassEq(const TargetRegisterClass *RC) cons 425 canCombineSubRegIndices(const TargetRegisterClass *RC, SmallVectorImpl<unsigned> &SubIndices, unsigned &NewSubIdx) const argument 453 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const argument 738 saveScavengerRegister(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, MachineBasicBlock::iterator &UseMI, const TargetRegisterClass *RC, unsigned Reg) const argument 796 SuperRegClassIterator(const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, bool IncludeSelf = false) argument [all...] |
/external/llvm/utils/release/ |
H A D | test-release.sh | 28 RC="" 68 -rc | --rc | -RC | --RC ) 70 RC="rc$1" 73 RC=final 134 if [ -z "$RC" ]; then 154 BuildDir=$BuildDir/$RC 189 if ! svn ls $Base_url/$proj/tags/RELEASE_$Release_no_dot/$RC > /dev/null 2>&1 ; then 190 echo "llvm $Release release candidate $RC doesn't exist!" 201 echo "# Exporting $proj $Release-RC [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | Thumb1InstrInfo.cpp | 54 const TargetRegisterClass *RC, 56 assert((RC == &ARM::tGPRRegClass || 60 if (RC == &ARM::tGPRRegClass || 82 const TargetRegisterClass *RC, 84 assert((RC == &ARM::tGPRRegClass || 88 if (RC == &ARM::tGPRRegClass || 52 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, bool isKill, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 80 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FI, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument
|
H A D | Thumb1InstrInfo.h | 49 const TargetRegisterClass *RC, 55 const TargetRegisterClass *RC,
|
H A D | Thumb2InstrInfo.h | 51 const TargetRegisterClass *RC, 57 const TargetRegisterClass *RC,
|
H A D | ARMBaseRegisterInfo.h | 108 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 115 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 118 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 120 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 123 ArrayRef<uint16_t> getRawAllocationOrder(const TargetRegisterClass *RC, 133 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
|
H A D | Thumb1RegisterInfo.h | 31 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 62 const TargetRegisterClass *RC,
|
/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.h | 84 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const; 87 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 98 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 100 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
|
/external/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 167 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 170 const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i]; local 171 const CodeGenRegister::Set &Regs = RC.getMembers(); 176 RC.buildRegUnitSet(RegUnits); 180 OS << "}, \t// " << RC.getName() << "\n"; 183 << " return RCWeightTable[RC->getID()];\n" 220 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n" 240 << " unsigned SetListStart = RCSetStartTable[RC->getID()];\n" 686 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 687 ArrayRef<Record*> Order = RC 720 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 825 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local 863 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 920 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 949 const CodeGenRegisterClass &RC = *RegisterClasses[rc]; local 965 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local 1001 const CodeGenRegisterClass &RC = *RegisterClasses[i]; local 1090 const CodeGenRegisterClass &RC = *RegisterClasses[rci]; local [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUInstrInfo.cpp | 142 const TargetRegisterClass *RC, 146 if (RC == &SPU::GPRCRegClass) 148 else if (RC == &SPU::R64CRegClass) 150 else if (RC == &SPU::R64FPRegClass) 152 else if (RC == &SPU::R32CRegClass) 154 else if (RC == &SPU::R32FPRegClass) 156 else if (RC == &SPU::R16CRegClass) 158 else if (RC == &SPU::R8CRegClass) 160 else if (RC == &SPU::VECREGRegClass) 175 const TargetRegisterClass *RC, 139 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument 172 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const argument [all...] |
H A D | SPUInstrInfo.h | 56 const TargetRegisterClass *RC, 63 const TargetRegisterClass *RC,
|
H A D | SPURegisterInfo.h | 54 virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC, argument 100 const TargetRegisterClass *RC,
|
/external/llvm/include/llvm/ |
H A D | InlineAsm.h | 253 static unsigned getFlagWordForRegClass(unsigned InputFlag, unsigned RC) { argument 254 // Store RC + 1, reserve the value 0 to mean 'no register class'. 255 ++RC; 256 assert(RC <= 0x7fff && "Too large register class ID"); 258 return InputFlag | (RC << 16); 291 /// class constraint. Sets RC to the register class ID. 292 static bool hasRegClassConstraint(unsigned Flag, unsigned &RC) { argument 297 // stores RC + 1. 300 RC = High - 1;
|
/external/clang/lib/AST/ |
H A D | RawCommentList.cpp | 204 void RawCommentList::addComment(const RawComment &RC, argument 206 if (RC.isInvalid()) 213 RC.getSourceRange().getBegin())) { 222 RC.getSourceRange().getBegin())) 226 PrevCommentEndLoc = RC.getSourceRange().getEnd(); 229 if (RC.isOrdinary()) 235 Comments.push_back(new (Allocator) RawComment(RC)); 241 const RawComment &C2 = RC; 259 Comments.push_back(new (Allocator) RawComment(RC));
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 73 const TargetRegisterClass *RC, 77 const TargetRegisterClass *RC, 129 const TargetRegisterClass *RC, 135 const TargetRegisterClass *RC,
|