1//===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMBASEREGISTERINFO_H 15#define ARMBASEREGISTERINFO_H 16 17#include "ARM.h" 18#include "llvm/Target/TargetRegisterInfo.h" 19 20#define GET_REGINFO_HEADER 21#include "ARMGenRegisterInfo.inc" 22 23namespace llvm { 24 class ARMSubtarget; 25 class ARMBaseInstrInfo; 26 class Type; 27 28/// Register allocation hints. 29namespace ARMRI { 30 enum { 31 RegPairOdd = 1, 32 RegPairEven = 2 33 }; 34} 35 36/// isARMArea1Register - Returns true if the register is a low register (r0-r7) 37/// or a stack/pc register that we should push/pop. 38static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { 39 using namespace ARM; 40 switch (Reg) { 41 case R0: case R1: case R2: case R3: 42 case R4: case R5: case R6: case R7: 43 case LR: case SP: case PC: 44 return true; 45 case R8: case R9: case R10: case R11: 46 // For iOS we want r7 and lr to be next to each other. 47 return !isIOS; 48 default: 49 return false; 50 } 51} 52 53static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { 54 using namespace ARM; 55 switch (Reg) { 56 case R8: case R9: case R10: case R11: 57 // iOS has this second area. 58 return isIOS; 59 default: 60 return false; 61 } 62} 63 64static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { 65 using namespace ARM; 66 switch (Reg) { 67 case D15: case D14: case D13: case D12: 68 case D11: case D10: case D9: case D8: 69 return true; 70 default: 71 return false; 72 } 73} 74 75class ARMBaseRegisterInfo : public ARMGenRegisterInfo { 76protected: 77 const ARMBaseInstrInfo &TII; 78 const ARMSubtarget &STI; 79 80 /// FramePtr - ARM physical register used as frame ptr. 81 unsigned FramePtr; 82 83 /// BasePtr - ARM physical register used as a base ptr in complex stack 84 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to 85 /// variable size stack objects. 86 unsigned BasePtr; 87 88 // Can be only subclassed. 89 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 90 const ARMSubtarget &STI); 91 92 // Return the opcode that implements 'Op', or 0 if no opcode 93 unsigned getOpcode(int Op) const; 94 95public: 96 /// Code Generation virtual methods... 97 const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const; 98 const uint32_t *getCallPreservedMask(CallingConv::ID) const; 99 100 BitVector getReservedRegs(const MachineFunction &MF) const; 101 102 /// canCombineSubRegIndices - Given a register class and a list of 103 /// subregister indices, return true if it's possible to combine the 104 /// subregister indices into one that corresponds to a larger 105 /// subregister. Return the new subregister index by reference. Note the 106 /// new index may be zero if the given subregisters can be combined to 107 /// form the whole register. 108 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC, 109 SmallVectorImpl<unsigned> &SubIndices, 110 unsigned &NewSubIdx) const; 111 112 const TargetRegisterClass* 113 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const; 114 const TargetRegisterClass* 115 getCrossCopyRegClass(const TargetRegisterClass *RC) const; 116 117 const TargetRegisterClass* 118 getLargestLegalSuperClass(const TargetRegisterClass *RC) const; 119 120 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 121 MachineFunction &MF) const; 122 123 ArrayRef<uint16_t> getRawAllocationOrder(const TargetRegisterClass *RC, 124 unsigned HintType, unsigned HintReg, 125 const MachineFunction &MF) const; 126 127 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg, 128 const MachineFunction &MF) const; 129 130 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 131 MachineFunction &MF) const; 132 133 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const; 134 135 bool hasBasePointer(const MachineFunction &MF) const; 136 137 bool canRealignStack(const MachineFunction &MF) const; 138 bool needsStackRealignment(const MachineFunction &MF) const; 139 int64_t getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const; 140 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const; 141 void materializeFrameBaseRegister(MachineBasicBlock *MBB, 142 unsigned BaseReg, int FrameIdx, 143 int64_t Offset) const; 144 void resolveFrameIndex(MachineBasicBlock::iterator I, 145 unsigned BaseReg, int64_t Offset) const; 146 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const; 147 148 bool cannotEliminateFrame(const MachineFunction &MF) const; 149 150 // Debug information queries. 151 unsigned getFrameRegister(const MachineFunction &MF) const; 152 unsigned getBaseRegister() const { return BasePtr; } 153 154 // Exception handling queries. 155 unsigned getEHExceptionRegister() const; 156 unsigned getEHHandlerRegister() const; 157 158 bool isLowRegister(unsigned Reg) const; 159 160 161 /// emitLoadConstPool - Emits a load from constpool to materialize the 162 /// specified immediate. 163 virtual void emitLoadConstPool(MachineBasicBlock &MBB, 164 MachineBasicBlock::iterator &MBBI, 165 DebugLoc dl, 166 unsigned DestReg, unsigned SubIdx, 167 int Val, 168 ARMCC::CondCodes Pred = ARMCC::AL, 169 unsigned PredReg = 0, 170 unsigned MIFlags = MachineInstr::NoFlags)const; 171 172 /// Code Generation virtual methods... 173 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const; 174 175 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const; 176 177 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const; 178 179 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const; 180 181 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const; 182 183 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF, 184 MachineBasicBlock &MBB, 185 MachineBasicBlock::iterator I) const; 186 187 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II, 188 int SPAdj, RegScavenger *RS = NULL) const; 189 190private: 191 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const; 192 193 unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const; 194}; 195 196} // end namespace llvm 197 198#endif 199