Searched refs:Reg (Results 1 - 25 of 205) sorted by relevance

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/external/qemu/target-i386/
H A Dops_sse_header.h21 #define Reg MMXReg macro
24 #define Reg XMMReg macro
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg) variable
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg) variable
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg) variable
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Re variable
42 DEF_HELPER_2(glue(psrad, SUFFIX), void, Reg, Reg) variable
43 DEF_HELPER_2(glue(pslld, SUFFIX), void, Reg, Reg) variable
44 DEF_HELPER_2(glue(psrlq, SUFFIX), void, Reg, Reg) variable
45 DEF_HELPER_2(glue(psllq, SUFFIX), void, Reg, Reg) variable
48 DEF_HELPER_2(glue(psrldq, SUFFIX), void, Reg, Reg) variable
49 DEF_HELPER_2(glue(pslldq, SUFFIX), void, Reg, Reg) variable
113 DEF_HELPER_2(glue(pmuludq, SUFFIX), void, Reg, Reg) variable
114 DEF_HELPER_2(glue(pmaddwd, SUFFIX), void, Reg, Reg) variable
116 DEF_HELPER_2(glue(psadbw, SUFFIX), void, Reg, Reg) variable
117 DEF_HELPER_3(glue(maskmov, SUFFIX), void, Reg, Reg, tl) variable
118 DEF_HELPER_2(glue(movl_mm_T0, SUFFIX), void, Reg, i32) variable
120 DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64) variable
124 DEF_HELPER_3(glue(pshufw, SUFFIX), void, Reg, Reg, int) variable
225 DEF_HELPER_2(glue(packsswb, SUFFIX), void, Reg, Reg) variable
226 DEF_HELPER_2(glue(packuswb, SUFFIX), void, Reg, Reg) variable
227 DEF_HELPER_2(glue(packssdw, SUFFIX), void, Reg, Reg) variable
237 DEF_HELPER_2(glue(punpcklqdq, SUFFIX), void, Reg, Reg) variable
238 DEF_HELPER_2(glue(punpckhqdq, SUFFIX), void, Reg, Reg) variable
265 DEF_HELPER_2(glue(phaddw, SUFFIX), void, Reg, Reg) variable
266 DEF_HELPER_2(glue(phaddd, SUFFIX), void, Reg, Reg) variable
267 DEF_HELPER_2(glue(phaddsw, SUFFIX), void, Reg, Reg) variable
268 DEF_HELPER_2(glue(phsubw, SUFFIX), void, Reg, Reg) variable
269 DEF_HELPER_2(glue(phsubd, SUFFIX), void, Reg, Reg) variable
270 DEF_HELPER_2(glue(phsubsw, SUFFIX), void, Reg, Reg) variable
271 DEF_HELPER_2(glue(pabsb, SUFFIX), void, Reg, Reg) variable
272 DEF_HELPER_2(glue(pabsw, SUFFIX), void, Reg, Reg) variable
273 DEF_HELPER_2(glue(pabsd, SUFFIX), void, Reg, Reg) variable
274 DEF_HELPER_2(glue(pmaddubsw, SUFFIX), void, Reg, Reg) variable
275 DEF_HELPER_2(glue(pmulhrsw, SUFFIX), void, Reg, Reg) variable
276 DEF_HELPER_2(glue(pshufb, SUFFIX), void, Reg, Reg) variable
277 DEF_HELPER_2(glue(psignb, SUFFIX), void, Reg, Reg) variable
278 DEF_HELPER_2(glue(psignw, SUFFIX), void, Reg, Reg) variable
279 DEF_HELPER_2(glue(psignd, SUFFIX), void, Reg, Reg) variable
280 DEF_HELPER_3(glue(palignr, SUFFIX), void, Reg, Reg, s32) variable
284 DEF_HELPER_2(glue(pblendvb, SUFFIX), void, Reg, Reg) variable
285 DEF_HELPER_2(glue(blendvps, SUFFIX), void, Reg, Reg) variable
286 DEF_HELPER_2(glue(blendvpd, SUFFIX), void, Reg, Reg) variable
287 DEF_HELPER_2(glue(ptest, SUFFIX), void, Reg, Reg) variable
288 DEF_HELPER_2(glue(pmovsxbw, SUFFIX), void, Reg, Reg) variable
289 DEF_HELPER_2(glue(pmovsxbd, SUFFIX), void, Reg, Reg) variable
290 DEF_HELPER_2(glue(pmovsxbq, SUFFIX), void, Reg, Reg) variable
291 DEF_HELPER_2(glue(pmovsxwd, SUFFIX), void, Reg, Reg) variable
292 DEF_HELPER_2(glue(pmovsxwq, SUFFIX), void, Reg, Reg) variable
293 DEF_HELPER_2(glue(pmovsxdq, SUFFIX), void, Reg, Reg) variable
294 DEF_HELPER_2(glue(pmovzxbw, SUFFIX), void, Reg, Reg) variable
295 DEF_HELPER_2(glue(pmovzxbd, SUFFIX), void, Reg, Reg) variable
296 DEF_HELPER_2(glue(pmovzxbq, SUFFIX), void, Reg, Reg) variable
297 DEF_HELPER_2(glue(pmovzxwd, SUFFIX), void, Reg, Reg) variable
298 DEF_HELPER_2(glue(pmovzxwq, SUFFIX), void, Reg, Reg) variable
299 DEF_HELPER_2(glue(pmovzxdq, SUFFIX), void, Reg, Reg) variable
300 DEF_HELPER_2(glue(pmuldq, SUFFIX), void, Reg, Reg) variable
301 DEF_HELPER_2(glue(pcmpeqq, SUFFIX), void, Reg, Reg) variable
302 DEF_HELPER_2(glue(packusdw, SUFFIX), void, Reg, Reg) variable
303 DEF_HELPER_2(glue(pminsb, SUFFIX), void, Reg, Reg) variable
304 DEF_HELPER_2(glue(pminsd, SUFFIX), void, Reg, Reg) variable
305 DEF_HELPER_2(glue(pminuw, SUFFIX), void, Reg, Reg) variable
306 DEF_HELPER_2(glue(pminud, SUFFIX), void, Reg, Reg) variable
307 DEF_HELPER_2(glue(pmaxsb, SUFFIX), void, Reg, Reg) variable
308 DEF_HELPER_2(glue(pmaxsd, SUFFIX), void, Reg, Reg) variable
309 DEF_HELPER_2(glue(pmaxuw, SUFFIX), void, Reg, Reg) variable
310 DEF_HELPER_2(glue(pmaxud, SUFFIX), void, Reg, Reg) variable
311 DEF_HELPER_2(glue(pmulld, SUFFIX), void, Reg, Reg) variable
312 DEF_HELPER_2(glue(phminposuw, SUFFIX), void, Reg, Reg) variable
313 DEF_HELPER_3(glue(roundps, SUFFIX), void, Reg, Reg, i32) variable
314 DEF_HELPER_3(glue(roundpd, SUFFIX), void, Reg, Reg, i32) variable
315 DEF_HELPER_3(glue(roundss, SUFFIX), void, Reg, Reg, i32) variable
316 DEF_HELPER_3(glue(roundsd, SUFFIX), void, Reg, Reg, i32) variable
317 DEF_HELPER_3(glue(blendps, SUFFIX), void, Reg, Reg, i32) variable
318 DEF_HELPER_3(glue(blendpd, SUFFIX), void, Reg, Reg, i32) variable
319 DEF_HELPER_3(glue(pblendw, SUFFIX), void, Reg, Reg, i32) variable
320 DEF_HELPER_3(glue(dpps, SUFFIX), void, Reg, Reg, i32) variable
321 DEF_HELPER_3(glue(dppd, SUFFIX), void, Reg, Reg, i32) variable
322 DEF_HELPER_3(glue(mpsadbw, SUFFIX), void, Reg, Reg, i32) variable
327 DEF_HELPER_2(glue(pcmpgtq, SUFFIX), void, Reg, Reg) variable
328 DEF_HELPER_3(glue(pcmpestri, SUFFIX), void, Reg, Reg, i32) variable
329 DEF_HELPER_3(glue(pcmpestrm, SUFFIX), void, Reg, Reg, i32) variable
330 DEF_HELPER_3(glue(pcmpistri, SUFFIX), void, Reg, Reg, i32) variable
331 DEF_HELPER_3(glue(pcmpistrm, SUFFIX), void, Reg, Reg, i32) variable
337 #undef Reg macro
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/external/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h38 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
44 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument
46 VRegInfo[Reg].first = RC;
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument
53 const TargetRegisterClass *OldRC = getRegClass(Reg);
61 setRegClass(Reg, NewRC);
66 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument
68 const TargetRegisterClass *OldRC = getRegClass(Reg);
76 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E;
90 setRegClass(Reg, NewRC);
104 unsigned Reg local
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H A DDeadMachineInstructionElim.cpp70 unsigned Reg = MO.getReg(); local
71 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
73 if (LivePhysRegs.test(Reg) || ReservedRegs.test(Reg))
76 if (!MRI->use_nodbg_empty(Reg))
110 unsigned Reg = *LOI; local
111 if (TargetRegisterInfo::isPhysicalRegister(Reg))
112 LivePhysRegs.set(Reg);
140 unsigned Reg = MO.getReg(); local
141 if (!TargetRegisterInfo::isVirtualRegister(Reg))
168 unsigned Reg = MO.getReg(); local
187 unsigned Reg = MO.getReg(); local
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H A DMachineInstrBundle.cpp131 unsigned Reg = MO.getReg(); local
132 if (!Reg)
134 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
135 if (LocalDefSet.count(Reg)) {
139 KilledDefSet.insert(Reg);
141 if (ExternUseSet.insert(Reg)) {
142 ExternUses.push_back(Reg);
144 UndefUseSet.insert(Reg);
148 KilledUseSet.insert(Reg);
154 unsigned Reg local
186 unsigned Reg = LocalDefs[i]; local
196 unsigned Reg = ExternUses[i]; local
252 analyzeVirtReg(unsigned Reg, SmallVectorImpl<std::pair<MachineInstr*, unsigned> > *Ops) argument
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H A DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument
62 unsigned Node = GroupNodeIndices[Reg];
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
76 Regs.push_back(Reg);
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument
107 IsLive(unsigned Reg) argument
161 unsigned Reg = *AI; local
177 unsigned Reg = *AI; local
190 unsigned Reg = *I; local
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H A DAllocationOrder.h56 unsigned Reg = *Pos++; local
57 if (Reg != Hint)
58 return Reg;
H A DCriticalAntiDepBreaker.cpp66 unsigned Reg = *AI; local
67 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
68 KillIndices[Reg] = BBSize;
69 DefIndices[Reg] = ~0u;
82 unsigned Reg = *AI; local
83 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
84 KillIndices[Reg] = BBSize;
85 DefIndices[Reg] = ~0u;
97 unsigned Reg = *AI; local
98 Classes[Reg]
188 unsigned Reg = MO.getReg(); local
251 unsigned Reg = MO.getReg(); local
282 unsigned Reg = MO.getReg(); local
581 unsigned Reg = MO.getReg(); local
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H A DLiveVariables.cpp182 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { argument
183 VarInfo &VRInfo = getVarInfo(Reg);
192 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, argument
197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg)) {
231 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { argument
232 MachineInstr *LastDef = PhysRegDef[Reg];
234 if (!LastDef && !PhysRegUse[Reg]) {
242 // All of the sub-registers must have been defined before the use of Reg!
244 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefReg
281 FindLastRefOrPartRef(unsigned Reg) argument
311 HandlePhysRegKill(unsigned Reg, MachineInstr *MI) argument
443 HandlePhysRegDef(unsigned Reg, MachineInstr *MI, SmallVector<unsigned, 4> &Defs) argument
489 unsigned Reg = Defs.back(); local
677 const unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
702 replaceKillInstruction(unsigned Reg, MachineInstr *OldMI, MachineInstr *NewMI) argument
715 unsigned Reg = MO.getReg(); local
740 isLiveIn(const MachineBasicBlock &MBB, unsigned Reg, MachineRegisterInfo &MRI) argument
758 isLiveOut(unsigned Reg, const MachineBasicBlock &MBB) argument
839 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
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H A DRegisterPressure.cpp272 /// Return true if Reg aliases a register in Regs SparseSet.
273 static bool hasRegAlias(unsigned Reg, SparseSet<unsigned> &Regs, argument
275 assert(!TargetRegisterInfo::isVirtualRegister(Reg) && "only for physregs");
276 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
282 /// Return true if Reg aliases a register in unsorted Regs SmallVector.
285 findRegAlias(unsigned Reg, SmallVectorImpl<unsigned> &Regs, argument
287 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
296 /// Return true if Reg can be inserted into Regs SmallVector. For virtual
299 findReg(unsigned Reg, bool isVReg, SmallVectorImpl<unsigned> &Regs, argument
302 return std::find(Regs.begin(), Regs.end(), Reg);
353 unsigned Reg = PhysRegOpers.DeadDefs[i-1]; local
376 discoverPhysLiveIn(unsigned Reg) argument
387 discoverPhysLiveOut(unsigned Reg) argument
398 discoverVirtLiveIn(unsigned Reg) argument
410 discoverVirtLiveOut(unsigned Reg) argument
465 unsigned Reg = PhysRegOpers.Defs[i]; local
472 unsigned Reg = VirtRegOpers.Defs[i]; local
481 unsigned Reg = PhysRegOpers.Uses[i]; local
488 unsigned Reg = VirtRegOpers.Uses[i]; local
531 unsigned Reg = PhysRegOpers.Uses[i]; local
541 unsigned Reg = VirtRegOpers.Uses[i]; local
559 unsigned Reg = PhysRegOpers.Defs[i]; local
566 unsigned Reg = VirtRegOpers.Defs[i]; local
684 unsigned Reg = PhysRegOpers.Uses[i]; local
689 unsigned Reg = VirtRegOpers.Uses[i]; local
730 findUseBetween(unsigned Reg, SlotIndex PriorUseIdx, SlotIndex NextUseIdx, const MachineRegisterInfo *MRI, const LiveIntervals *LIS) argument
763 unsigned Reg = VirtRegOpers.Uses[i]; local
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H A DRegisterScavenging.cpp37 void RegScavenger::setUsed(unsigned Reg) { argument
38 RegsAvailable.reset(Reg);
40 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
44 bool RegScavenger::isAliasUsed(unsigned Reg) const {
45 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
112 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { argument
113 BV.set(Reg);
114 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
154 unsigned Reg = MO.getReg(); local
155 if (!Reg || isReserve
179 unsigned Reg = MO.getReg(); local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.h74 bool isAllocated(unsigned Reg) const {
75 return UsedRegs[Reg/32] & (1 << (Reg&31));
121 unsigned AllocateReg(unsigned Reg) { argument
122 if (isAllocated(Reg)) return 0;
123 MarkAllocated(Reg);
124 return Reg;
128 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
129 if (isAllocated(Reg)) return 0;
130 MarkAllocated(Reg);
144 unsigned Reg = Regs[FirstUnalloc]; local
157 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
29 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
30 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
36 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { argument
39 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
40 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/external/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h77 return MO->Contents.Reg.Next;
188 /// Reg are Debug instructions.
267 MachineInstr *getVRegDef(unsigned Reg) const;
272 MachineInstr *getUniqueVRegDef(unsigned Reg) const;
278 void clearKillFlags(unsigned Reg) const;
295 const TargetRegisterClass *getRegClass(unsigned Reg) const {
296 return VRegInfo[Reg].first;
301 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
310 const TargetRegisterClass *constrainRegClass(unsigned Reg,
314 /// recomputeRegClass - Try to find a legal super-class of Reg'
338 setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) argument
381 setPhysRegUsed(unsigned Reg) argument
395 setPhysRegUnused(unsigned Reg) argument
437 addLiveIn(unsigned Reg, unsigned vreg = 0) argument
440 addLiveOut(unsigned Reg) argument
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H A DLiveVariables.h108 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
109 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
112 unsigned Reg,
158 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
161 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
166 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
167 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
173 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
178 MachineInstr *FindLastPartialDef(unsigned Reg,
289 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
307 isPHIJoin(unsigned Reg) argument
310 setPHIJoin(unsigned Reg) argument
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H A DRegisterScavenging.h130 void setUsed(unsigned Reg);
133 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }
137 bool isUsed(unsigned Reg) const {
138 return !RegsAvailable.test(Reg) || ReservedRegs.test(Reg);
141 /// isAliasUsed - Is Reg or an alias currently in use?
142 bool isAliasUsed(unsigned Reg) const;
153 /// Add Reg and all its sub-registers to BV.
154 void addRegWithSubRegs(BitVector &BV, unsigned Reg);
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H A DCallingConvLower.h190 bool isAllocated(unsigned Reg) const {
191 return UsedRegs[Reg/32] & (1 << (Reg&31));
242 unsigned AllocateReg(unsigned Reg) { argument
243 if (isAllocated(Reg)) return 0;
244 MarkAllocated(Reg);
245 return Reg;
249 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { argument
250 if (isAllocated(Reg)) return 0;
251 MarkAllocated(Reg);
265 unsigned Reg = Regs[FirstUnalloc]; local
278 unsigned Reg = Regs[FirstUnalloc], ShadowReg = ShadowRegs[FirstUnalloc]; local
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H A DLiveIntervalAnalysis.h112 LiveInterval &getInterval(unsigned Reg) { argument
113 LiveInterval *LI = VirtRegIntervals[Reg];
118 const LiveInterval &getInterval(unsigned Reg) const {
119 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
122 bool hasInterval(unsigned Reg) const {
123 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
139 LiveInterval &getOrCreateInterval(unsigned Reg) { argument
140 if (!hasInterval(Reg)) {
141 VirtRegIntervals.grow(Reg);
148 removeInterval(unsigned Reg) argument
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H A DFunctionLoweringInfo.h151 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) { argument
152 if (!LiveOutRegInfo.inBounds(Reg))
155 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
167 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
170 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits, argument
176 LiveOutRegInfo.grow(Reg);
177 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
195 unsigned Reg = It->second; local
196 LiveOutRegInfo.grow(Reg);
197 LiveOutRegInfo[Reg]
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/external/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp63 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
87 unsigned Reg = MI->getOperand(1).getReg(); local
88 if (TargetRegisterInfo::isPhysicalRegister(Reg))
92 MachineInstr *DefMI = MRI->getVRegDef(Reg);
97 Reg = DefMI->getOperand(1).getReg();
98 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
99 DefMI = MRI->getVRegDef(Reg);
103 Reg = DefMI->getOperand(2).getReg();
104 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
105 DefMI = MRI->getVRegDef(Reg);
115 unsigned Reg = MI->getOperand(0).getReg(); local
138 hasRAWHazard(unsigned Reg, MachineInstr *MI) const argument
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H A DARMBaseRegisterInfo.h38 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { argument
40 switch (Reg) {
53 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { argument
55 switch (Reg) {
64 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { argument
66 switch (Reg) {
127 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
130 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
158 bool isLowRegister(unsigned Reg) const;
173 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) cons
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H A DARMCallingConv.h34 if (unsigned Reg = State.AllocateReg(RegList, 4))
35 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
49 if (unsigned Reg = State.AllocateReg(RegList, 4))
50 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
78 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2); local
79 if (Reg == 0) {
93 if (HiRegList[i] == Reg)
100 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
123 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2); local
124 if (Reg
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/external/llvm/lib/Target/Mips/
H A DMipsRegisterInfo.cpp102 for (RegIter Reg = Mips::AFGR64RegClass.begin(),
103 EReg = Mips::AFGR64RegClass.end(); Reg != EReg; ++Reg)
104 Reserved.set(*Reg);
107 for (RegIter Reg = Mips::CPU64RegsRegClass.begin(),
108 EReg = Mips::CPU64RegsRegClass.end(); Reg != EReg; ++Reg)
109 Reserved.set(*Reg);
111 for (RegIter Reg = Mips::FGR64RegClass.begin(),
112 EReg = Mips::FGR64RegClass.end(); Reg !
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/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h75 bool contains(unsigned Reg) const {
76 return MC->contains(Reg);
159 /// For all Reg in SuperRC:
160 /// this->contains(Reg:Idx)
247 /// returns true if Reg is in the range used for stack slots.
253 static bool isStackSlot(unsigned Reg) { argument
254 return int(Reg) >= (1 << 30);
259 static int stackSlot2Index(unsigned Reg) { argument
260 assert(isStackSlot(Reg) && "Not a stack slot");
261 return int(Reg
273 isPhysicalRegister(unsigned Reg) argument
280 isVirtualRegister(unsigned Reg) argument
287 virtReg2Index(unsigned Reg) argument
353 hasRegUnit(unsigned Reg, unsigned RegUnit) const argument
414 getMatchingSuperReg(unsigned Reg, unsigned SubIdx, const TargetRegisterClass *RC) const argument
603 ResolveRegAllocHint(unsigned Type, unsigned Reg, const MachineFunction &MF) const argument
624 UpdateRegAllocHint(unsigned Reg, unsigned NewReg, MachineFunction &MF) const argument
661 hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const argument
848 unsigned Reg; member in class:llvm::PrintReg
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/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h67 bool contains(unsigned Reg) const {
68 unsigned InByte = Reg % 8;
69 unsigned Byte = Reg / 8;
312 unsigned getSubReg(unsigned Reg, unsigned Idx) const;
315 /// Reg so its sub-register of index SubIdx is Reg.
316 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
387 /// MCSubRegIterator enumerates all sub-registers of Reg.
390 MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
391 init(Reg, MCR
409 MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI, bool IncludeSelf) argument
436 MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) argument
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