1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARM.h" 19#include "ARMSubtarget.h" 20#include "llvm/Target/TargetLowering.h" 21#include "llvm/Target/TargetRegisterInfo.h" 22#include "llvm/CodeGen/FastISel.h" 23#include "llvm/CodeGen/SelectionDAG.h" 24#include "llvm/CodeGen/CallingConvLower.h" 25#include <vector> 26 27namespace llvm { 28 class ARMConstantPoolValue; 29 30 namespace ARMISD { 31 // ARM Specific DAG Nodes 32 enum NodeType { 33 // Start the numbering where the builtin ops and target ops leave off. 34 FIRST_NUMBER = ISD::BUILTIN_OP_END, 35 36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 37 // TargetExternalSymbol, and TargetGlobalAddress. 38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in 39 // DYN mode. 40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 41 // PIC mode. 42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 43 44 // Add pseudo op to model memcpy for struct byval. 45 COPY_STRUCT_BYVAL, 46 47 CALL, // Function call. 48 CALL_PRED, // Function call that's predicable. 49 CALL_NOLINK, // Function call with branch not branch-and-link. 50 tCALL, // Thumb function call. 51 BRCOND, // Conditional branch. 52 BR_JT, // Jumptable branch. 53 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 54 RET_FLAG, // Return with a flag operand. 55 56 PIC_ADD, // Add with a PC operand and a PIC label. 57 58 CMP, // ARM compare instructions. 59 CMN, // ARM CMN instructions. 60 CMPZ, // ARM compare that sets only Z flag. 61 CMPFP, // ARM VFP compare instruction, sets FPSCR. 62 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 63 FMSTAT, // ARM fmstat instruction. 64 65 CMOV, // ARM conditional move instructions. 66 67 BCC_i64, 68 69 RBIT, // ARM bitreverse instruction 70 71 FTOSI, // FP to sint within a FP register. 72 FTOUI, // FP to uint within a FP register. 73 SITOF, // sint to FP within a FP register. 74 UITOF, // uint to FP within a FP register. 75 76 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 77 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 78 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 79 80 ADDC, // Add with carry 81 ADDE, // Add using carry 82 SUBC, // Sub with carry 83 SUBE, // Sub using carry 84 85 VMOVRRD, // double to two gprs. 86 VMOVDRR, // Two gprs to double. 87 88 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 89 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 90 91 TC_RETURN, // Tail call return pseudo. 92 93 THREAD_POINTER, 94 95 DYN_ALLOC, // Dynamic allocation on the stack. 96 97 MEMBARRIER, // Memory barrier (DMB) 98 MEMBARRIER_MCR, // Memory barrier (MCR) 99 100 PRELOAD, // Preload 101 102 VCEQ, // Vector compare equal. 103 VCEQZ, // Vector compare equal to zero. 104 VCGE, // Vector compare greater than or equal. 105 VCGEZ, // Vector compare greater than or equal to zero. 106 VCLEZ, // Vector compare less than or equal to zero. 107 VCGEU, // Vector compare unsigned greater than or equal. 108 VCGT, // Vector compare greater than. 109 VCGTZ, // Vector compare greater than zero. 110 VCLTZ, // Vector compare less than zero. 111 VCGTU, // Vector compare unsigned greater than. 112 VTST, // Vector test bits. 113 114 // Vector shift by immediate: 115 VSHL, // ...left 116 VSHRs, // ...right (signed) 117 VSHRu, // ...right (unsigned) 118 VSHLLs, // ...left long (signed) 119 VSHLLu, // ...left long (unsigned) 120 VSHLLi, // ...left long (with maximum shift count) 121 VSHRN, // ...right narrow 122 123 // Vector rounding shift by immediate: 124 VRSHRs, // ...right (signed) 125 VRSHRu, // ...right (unsigned) 126 VRSHRN, // ...right narrow 127 128 // Vector saturating shift by immediate: 129 VQSHLs, // ...left (signed) 130 VQSHLu, // ...left (unsigned) 131 VQSHLsu, // ...left (signed to unsigned) 132 VQSHRNs, // ...right narrow (signed) 133 VQSHRNu, // ...right narrow (unsigned) 134 VQSHRNsu, // ...right narrow (signed to unsigned) 135 136 // Vector saturating rounding shift by immediate: 137 VQRSHRNs, // ...right narrow (signed) 138 VQRSHRNu, // ...right narrow (unsigned) 139 VQRSHRNsu, // ...right narrow (signed to unsigned) 140 141 // Vector shift and insert: 142 VSLI, // ...left 143 VSRI, // ...right 144 145 // Vector get lane (VMOV scalar to ARM core register) 146 // (These are used for 8- and 16-bit element types only.) 147 VGETLANEu, // zero-extend vector extract element 148 VGETLANEs, // sign-extend vector extract element 149 150 // Vector move immediate and move negated immediate: 151 VMOVIMM, 152 VMVNIMM, 153 154 // Vector move f32 immediate: 155 VMOVFPIMM, 156 157 // Vector duplicate: 158 VDUP, 159 VDUPLANE, 160 161 // Vector shuffles: 162 VEXT, // extract 163 VREV64, // reverse elements within 64-bit doublewords 164 VREV32, // reverse elements within 32-bit words 165 VREV16, // reverse elements within 16-bit halfwords 166 VZIP, // zip (interleave) 167 VUZP, // unzip (deinterleave) 168 VTRN, // transpose 169 VTBL1, // 1-register shuffle with mask 170 VTBL2, // 2-register shuffle with mask 171 172 // Vector multiply long: 173 VMULLs, // ...signed 174 VMULLu, // ...unsigned 175 176 UMLAL, // 64bit Unsigned Accumulate Multiply 177 SMLAL, // 64bit Signed Accumulate Multiply 178 179 // Operands of the standard BUILD_VECTOR node are not legalized, which 180 // is fine if BUILD_VECTORs are always lowered to shuffles or other 181 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 182 // operands need to be legalized. Define an ARM-specific version of 183 // BUILD_VECTOR for this purpose. 184 BUILD_VECTOR, 185 186 // Floating-point max and min: 187 FMAX, 188 FMIN, 189 190 // Bit-field insert 191 BFI, 192 193 // Vector OR with immediate 194 VORRIMM, 195 // Vector AND with NOT of immediate 196 VBICIMM, 197 198 // Vector bitwise select 199 VBSL, 200 201 // Vector load N-element structure to all lanes: 202 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 203 VLD3DUP, 204 VLD4DUP, 205 206 // NEON loads with post-increment base updates: 207 VLD1_UPD, 208 VLD2_UPD, 209 VLD3_UPD, 210 VLD4_UPD, 211 VLD2LN_UPD, 212 VLD3LN_UPD, 213 VLD4LN_UPD, 214 VLD2DUP_UPD, 215 VLD3DUP_UPD, 216 VLD4DUP_UPD, 217 218 // NEON stores with post-increment base updates: 219 VST1_UPD, 220 VST2_UPD, 221 VST3_UPD, 222 VST4_UPD, 223 VST2LN_UPD, 224 VST3LN_UPD, 225 VST4LN_UPD, 226 227 // 64-bit atomic ops (value split into two registers) 228 ATOMADD64_DAG, 229 ATOMSUB64_DAG, 230 ATOMOR64_DAG, 231 ATOMXOR64_DAG, 232 ATOMAND64_DAG, 233 ATOMNAND64_DAG, 234 ATOMSWAP64_DAG, 235 ATOMCMPXCHG64_DAG 236 }; 237 } 238 239 /// Define some predicates that are used for node matching. 240 namespace ARM { 241 bool isBitFieldInvertedMask(unsigned v); 242 } 243 244 //===--------------------------------------------------------------------===// 245 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 246 247 class ARMTargetLowering : public TargetLowering { 248 public: 249 explicit ARMTargetLowering(TargetMachine &TM); 250 251 virtual unsigned getJumpTableEncoding(void) const; 252 253 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 254 255 /// ReplaceNodeResults - Replace the results of node with an illegal result 256 /// type with new values built out of custom code. 257 /// 258 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 259 SelectionDAG &DAG) const; 260 261 virtual const char *getTargetNodeName(unsigned Opcode) const; 262 263 virtual bool isSelectSupported(SelectSupportKind Kind) const { 264 // ARM does not support scalar condition selects on vectors. 265 return (Kind != ScalarCondVectorVal); 266 } 267 268 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 269 virtual EVT getSetCCResultType(EVT VT) const; 270 271 virtual MachineBasicBlock * 272 EmitInstrWithCustomInserter(MachineInstr *MI, 273 MachineBasicBlock *MBB) const; 274 275 virtual void 276 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 277 278 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 279 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 280 281 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const; 282 283 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 284 /// unaligned memory accesses. of the specified type. 285 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 286 287 virtual EVT getOptimalMemOpType(uint64_t Size, 288 unsigned DstAlign, unsigned SrcAlign, 289 bool IsZeroVal, 290 bool MemcpyStrSrc, 291 MachineFunction &MF) const; 292 293 /// isLegalAddressingMode - Return true if the addressing mode represented 294 /// by AM is legal for this target, for a load/store of the specified type. 295 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 296 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 297 298 /// isLegalICmpImmediate - Return true if the specified immediate is legal 299 /// icmp immediate, that is the target has icmp instructions which can 300 /// compare a register against the immediate without having to materialize 301 /// the immediate into a register. 302 virtual bool isLegalICmpImmediate(int64_t Imm) const; 303 304 /// isLegalAddImmediate - Return true if the specified immediate is legal 305 /// add immediate, that is the target has add instructions which can 306 /// add a register and the immediate without having to materialize 307 /// the immediate into a register. 308 virtual bool isLegalAddImmediate(int64_t Imm) const; 309 310 /// getPreIndexedAddressParts - returns true by value, base pointer and 311 /// offset pointer and addressing mode by reference if the node's address 312 /// can be legally represented as pre-indexed load / store address. 313 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 314 SDValue &Offset, 315 ISD::MemIndexedMode &AM, 316 SelectionDAG &DAG) const; 317 318 /// getPostIndexedAddressParts - returns true by value, base pointer and 319 /// offset pointer and addressing mode by reference if this node can be 320 /// combined with a load / store to form a post-indexed load / store. 321 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 322 SDValue &Base, SDValue &Offset, 323 ISD::MemIndexedMode &AM, 324 SelectionDAG &DAG) const; 325 326 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 327 APInt &KnownZero, 328 APInt &KnownOne, 329 const SelectionDAG &DAG, 330 unsigned Depth) const; 331 332 333 virtual bool ExpandInlineAsm(CallInst *CI) const; 334 335 ConstraintType getConstraintType(const std::string &Constraint) const; 336 337 /// Examine constraint string and operand type and determine a weight value. 338 /// The operand object must already have been set up with the operand type. 339 ConstraintWeight getSingleConstraintMatchWeight( 340 AsmOperandInfo &info, const char *constraint) const; 341 342 std::pair<unsigned, const TargetRegisterClass*> 343 getRegForInlineAsmConstraint(const std::string &Constraint, 344 EVT VT) const; 345 346 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 347 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 348 /// true it means one of the asm constraint of the inline asm instruction 349 /// being processed is 'm'. 350 virtual void LowerAsmOperandForConstraint(SDValue Op, 351 std::string &Constraint, 352 std::vector<SDValue> &Ops, 353 SelectionDAG &DAG) const; 354 355 const ARMSubtarget* getSubtarget() const { 356 return Subtarget; 357 } 358 359 /// getRegClassFor - Return the register class that should be used for the 360 /// specified value type. 361 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const; 362 363 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 364 /// be used for loads / stores from the global. 365 virtual unsigned getMaximalGlobalOffset() const; 366 367 /// createFastISel - This method returns a target specific FastISel object, 368 /// or null if the target does not support "fast" ISel. 369 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 370 const TargetLibraryInfo *libInfo) const; 371 372 Sched::Preference getSchedulingPreference(SDNode *N) const; 373 374 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 375 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 376 377 /// isFPImmLegal - Returns true if the target can instruction select the 378 /// specified FP immediate natively. If false, the legalizer will 379 /// materialize the FP immediate as a load from a constant pool. 380 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 381 382 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 383 const CallInst &I, 384 unsigned Intrinsic) const; 385 protected: 386 std::pair<const TargetRegisterClass*, uint8_t> 387 findRepresentativeClass(EVT VT) const; 388 389 private: 390 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 391 /// make the right decision when generating code for different targets. 392 const ARMSubtarget *Subtarget; 393 394 const TargetRegisterInfo *RegInfo; 395 396 const InstrItineraryData *Itins; 397 398 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 399 /// 400 unsigned ARMPCLabelIndex; 401 402 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 403 void addDRTypeForNEON(MVT VT); 404 void addQRTypeForNEON(MVT VT); 405 406 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 407 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 408 SDValue Chain, SDValue &Arg, 409 RegsToPassVector &RegsToPass, 410 CCValAssign &VA, CCValAssign &NextVA, 411 SDValue &StackPtr, 412 SmallVector<SDValue, 8> &MemOpChains, 413 ISD::ArgFlagsTy Flags) const; 414 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 415 SDValue &Root, SelectionDAG &DAG, 416 DebugLoc dl) const; 417 418 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 419 bool isVarArg) const; 420 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 421 DebugLoc dl, SelectionDAG &DAG, 422 const CCValAssign &VA, 423 ISD::ArgFlagsTy Flags) const; 424 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 425 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 426 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 427 const ARMSubtarget *Subtarget) const; 428 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 429 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 430 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 431 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 432 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 433 SelectionDAG &DAG) const; 434 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 435 SelectionDAG &DAG, 436 TLSModel::Model model) const; 437 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 438 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 439 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 440 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 441 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 442 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 443 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 444 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 445 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 446 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 447 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 448 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 449 const ARMSubtarget *ST) const; 450 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 451 const ARMSubtarget *ST) const; 452 453 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 454 455 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 456 CallingConv::ID CallConv, bool isVarArg, 457 const SmallVectorImpl<ISD::InputArg> &Ins, 458 DebugLoc dl, SelectionDAG &DAG, 459 SmallVectorImpl<SDValue> &InVals) const; 460 461 virtual SDValue 462 LowerFormalArguments(SDValue Chain, 463 CallingConv::ID CallConv, bool isVarArg, 464 const SmallVectorImpl<ISD::InputArg> &Ins, 465 DebugLoc dl, SelectionDAG &DAG, 466 SmallVectorImpl<SDValue> &InVals) const; 467 468 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 469 DebugLoc dl, SDValue &Chain, unsigned ArgOffset) 470 const; 471 472 void computeRegArea(CCState &CCInfo, MachineFunction &MF, 473 unsigned &VARegSize, unsigned &VARegSaveSize) const; 474 475 virtual SDValue 476 LowerCall(TargetLowering::CallLoweringInfo &CLI, 477 SmallVectorImpl<SDValue> &InVals) const; 478 479 /// HandleByVal - Target-specific cleanup for ByVal support. 480 virtual void HandleByVal(CCState *, unsigned &) const; 481 482 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 483 /// for tail call optimization. Targets which want to do tail call 484 /// optimization should implement this function. 485 bool IsEligibleForTailCallOptimization(SDValue Callee, 486 CallingConv::ID CalleeCC, 487 bool isVarArg, 488 bool isCalleeStructRet, 489 bool isCallerStructRet, 490 const SmallVectorImpl<ISD::OutputArg> &Outs, 491 const SmallVectorImpl<SDValue> &OutVals, 492 const SmallVectorImpl<ISD::InputArg> &Ins, 493 SelectionDAG& DAG) const; 494 virtual SDValue 495 LowerReturn(SDValue Chain, 496 CallingConv::ID CallConv, bool isVarArg, 497 const SmallVectorImpl<ISD::OutputArg> &Outs, 498 const SmallVectorImpl<SDValue> &OutVals, 499 DebugLoc dl, SelectionDAG &DAG) const; 500 501 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 502 503 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 504 505 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 506 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 507 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 508 SelectionDAG &DAG, DebugLoc dl) const; 509 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 510 511 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 512 513 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 514 MachineBasicBlock *BB, 515 unsigned Size) const; 516 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 517 MachineBasicBlock *BB, 518 unsigned Size, 519 unsigned BinOpcode) const; 520 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, 521 MachineBasicBlock *BB, 522 unsigned Op1, 523 unsigned Op2, 524 bool NeedsCarry = false, 525 bool IsCmpxchg = false) const; 526 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, 527 MachineBasicBlock *BB, 528 unsigned Size, 529 bool signExtend, 530 ARMCC::CondCodes Cond) const; 531 532 void SetupEntryBlockForSjLj(MachineInstr *MI, 533 MachineBasicBlock *MBB, 534 MachineBasicBlock *DispatchBB, int FI) const; 535 536 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 537 MachineBasicBlock *MBB) const; 538 539 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 540 541 MachineBasicBlock *EmitStructByval(MachineInstr *MI, 542 MachineBasicBlock *MBB) const; 543 }; 544 545 enum NEONModImmType { 546 VMOVModImm, 547 VMVNModImm, 548 OtherModImm 549 }; 550 551 552 namespace ARM { 553 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 554 const TargetLibraryInfo *libInfo); 555 } 556} 557 558#endif // ARMISELLOWERING_H 559