SPUISelLowering.h revision 94bd57e154088f2d45c465e73f896f64f6da4ade 
1//===-- SPUISelLowering.h - Cell SPU DAG Lowering Interface -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that Cell SPU uses to lower LLVM code into
11// a selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef SPU_ISELLOWERING_H
16#define SPU_ISELLOWERING_H
17
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/CodeGen/SelectionDAG.h"
20#include "SPU.h"
21
22namespace llvm {
23  namespace SPUISD {
24    enum NodeType {
25      // Start the numbering where the builting ops and target ops leave off.
26      FIRST_NUMBER = ISD::BUILTIN_OP_END,
27
28      // Pseudo instructions:
29      RET_FLAG,                 ///< Return with flag, matched by bi instruction
30
31      Hi,                       ///< High address component (upper 16)
32      Lo,                       ///< Low address component (lower 16)
33      PCRelAddr,                ///< Program counter relative address
34      AFormAddr,                ///< A-form address (local store)
35      IndirectAddr,             ///< D-Form "imm($r)" and X-form "$r($r)"
36
37      LDRESULT,                 ///< Load result (value, chain)
38      CALL,                     ///< CALL instruction
39      SHUFB,                    ///< Vector shuffle (permute)
40      SHUFFLE_MASK,             ///< Shuffle mask
41      CNTB,                     ///< Count leading ones in bytes
42      PREFSLOT2VEC,             ///< Promote scalar->vector
43      VEC2PREFSLOT,             ///< Extract element 0
44      SHLQUAD_L_BITS,           ///< Rotate quad left, by bits
45      SHLQUAD_L_BYTES,          ///< Rotate quad left, by bytes
46      VEC_SHL,                  ///< Vector shift left
47      VEC_SRL,                  ///< Vector shift right (logical)
48      VEC_SRA,                  ///< Vector shift right (arithmetic)
49      VEC_ROTL,                 ///< Vector rotate left
50      VEC_ROTR,                 ///< Vector rotate right
51      ROTBYTES_LEFT,            ///< Rotate bytes (loads -> ROTQBYI)
52      ROTBYTES_LEFT_BITS,       ///< Rotate bytes left by bit shift count
53      SELECT_MASK,              ///< Select Mask (FSM, FSMB, FSMH, FSMBI)
54      SELB,                     ///< Select bits -> (b & mask) | (a & ~mask)
55      // Markers: These aren't used to generate target-dependent nodes, but
56      // are used during instruction selection.
57      ADD64_MARKER,             ///< i64 addition marker
58      SUB64_MARKER,             ///< i64 subtraction marker
59      MUL64_MARKER,             ///< i64 multiply marker
60      LAST_SPUISD               ///< Last user-defined instruction
61    };
62  }
63
64  /// Predicates that are used for node matching:
65  namespace SPU {
66    SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG,
67                             MVT ValueType);
68    SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG,
69                             MVT ValueType);
70    SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG,
71                             MVT ValueType);
72    SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG,
73                            MVT ValueType);
74    SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG,
75                              MVT ValueType);
76    SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG);
77    SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG);
78
79    SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG,
80                              const SPUTargetMachine &TM);
81
82    SDValue getBorrowGenerateShufMask(SelectionDAG &DAG);
83    SDValue getCarryGenerateShufMask(SelectionDAG &DAG);
84  }
85
86  class SPUTargetMachine;            // forward dec'l.
87
88  class SPUTargetLowering :
89    public TargetLowering
90  {
91    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
92    int ReturnAddrIndex;              // FrameIndex for return slot.
93    SPUTargetMachine &SPUTM;
94
95  public:
96    //! The venerable constructor
97    /*!
98     This is where the CellSPU backend sets operation handling (i.e., legal,
99     custom, expand or promote.)
100     */
101    SPUTargetLowering(SPUTargetMachine &TM);
102
103    //! Get the target machine
104    SPUTargetMachine &getSPUTargetMachine() {
105      return SPUTM;
106    }
107
108    /// getTargetNodeName() - This method returns the name of a target specific
109    /// DAG node.
110    virtual const char *getTargetNodeName(unsigned Opcode) const;
111
112    /// getSetCCResultType - Return the ValueType for ISD::SETCC
113    virtual MVT getSetCCResultType(MVT VT) const;
114
115    //! Custom lowering hooks
116    virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
117
118    //! Custom lowering hook for nodes with illegal result types.
119    virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
120                                    SelectionDAG &DAG);
121
122    virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
123
124    virtual void computeMaskedBitsForTargetNode(const SDValue Op,
125                                                const APInt &Mask,
126                                                APInt &KnownZero,
127                                                APInt &KnownOne,
128                                                const SelectionDAG &DAG,
129                                                unsigned Depth = 0) const;
130
131    virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
132                                                   unsigned Depth = 0) const;
133
134    ConstraintType getConstraintType(const std::string &ConstraintLetter) const;
135
136    std::pair<unsigned, const TargetRegisterClass*>
137      getRegForInlineAsmConstraint(const std::string &Constraint,
138                                   MVT VT) const;
139
140    void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
141                                      bool hasMemory,
142                                      std::vector<SDValue> &Ops,
143                                      SelectionDAG &DAG) const;
144
145    /// isLegalAddressImmediate - Return true if the integer value can be used
146    /// as the offset of the target addressing mode.
147    virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
148    virtual bool isLegalAddressImmediate(GlobalValue *) const;
149
150    virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
151  };
152}
153
154#endif
155