| 95a9d937728ca9cf2bf44f86ff1184df318b3bd7 |
|
06-Jun-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Round 2 of dead private variable removal.
LLVM is now -Wunused-private-field clean except for
- lib/MC/MCDisassembler/Disassembler.h. Not sure why it keeps all those unaccessible fields.
- gtest.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| d2ea0e10cbd158c93fb870cdd03001b9cd1156b8 |
|
25-May-2012 |
Justin Holewinski <jholewinski@nvidia.com> |
Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCall
to pass around a struct instead of a large set of individual values. This
cleans up the interface and allows more information to be added to the struct
for future targets without requiring changes to each and every target.
NV_CONTRIB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
|
28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| ec52aaa12f57896fc806e849fa21a61603050ac4 |
|
28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.
Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.
rdar://8979299
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 28b77e968d2b01fc9da724762bd8ddcd80650e32 |
|
06-Sep-2011 |
Duncan Sands <baldrick@free.fr> |
Add codegen support for vector select (in the IR this means a select
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| db125cfaf57cc83e7dd7453de2d509bc8efd0e5e |
|
18-Jul-2011 |
Chris Lattner <sabre@nondot.org> |
land David Blaikie's patch to de-constify Type, with a few tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 100c83341676d8aae8fc34b5452563ed08b14f3e |
|
03-Jun-2011 |
Eric Christopher <echristo@apple.com> |
Have LowerOperandForConstraint handle multiple character constraints.
Part of rdar://9119939
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| fc5d305597ea6336d75bd7f3b741e8d57d6a5105 |
|
06-May-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Make the logic for determining function alignment more explicit. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| be2119e8e2bc7006cfd638a24367acbfda625d16 |
|
07-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 95771afbfd604ad003fa3723cac66c9370fed55d |
|
25-Feb-2011 |
Owen Anderson <resistor@mac.com> |
Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| b00f24b13c49fe1d7151a143fbb6213b3615c7ad |
|
29-Nov-2010 |
Kalle Raiskila <kalle.raiskila@nokia.com> |
Allow machine LICM to do its job on SPU.
-return a sensible value for register pressure
-add pattern to 'ila' instrucion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 7ea1ab5f41299563eb648aed159cfaff09e774d8 |
|
12-Nov-2010 |
Kalle Raiskila <kalle.raiskila@nokia.com> |
Fix memory access lowering on SPU, adding
support for the case where alignment<value size.
These cases were silently miscompiled before this patch.
Now they are overly verbose -especially storing is- and
any front-end should still avoid misaligned memory
accesses as much as possible. The bit juggling algorithm
added here probably has some room for improvement still.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 44ab89eb376af838d1123293a79975aede501464 |
|
29-Oct-2010 |
John Thompson <John.Thompson.JTSoftware@gmail.com> |
Inline asm multiple alternative constraints development phase 2 - improved basic logic, added initial platform support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 8a52fa674b78ff0fdc04b1bf1124aa57c007f8ff |
|
07-Oct-2010 |
Kalle Raiskila <kalle.raiskila@nokia.com> |
Implement two virtual functions in SPUTargetLowering.
Before the implementation of isLegalAddressingMode, some rare cases
of code were miscompiled if optimized with the LoopStrengthReduce pass.
It is unclear (to me) if LSR is "allowed" to produce wrong code with a
bad TargetLowering, or if the bug is elsewhere and this patch just
hides it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| f53fdc2e455e7e85a4b1278dd9027b237f6b829a |
|
24-Aug-2010 |
Kalle Raiskila <kalle.raiskila@nokia.com> |
Remove some dead code from SPU BE that remained
from 64bit vector support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 99534bb81a0d945edd61d4db17549bde8449f94c |
|
09-Aug-2010 |
Kalle Raiskila <kalle.raiskila@nokia.com> |
Have SPU handle halfvec stores aligned by 8 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| c9403659a98bf6487ab6fbf40b81628b5695c02e |
|
07-Jul-2010 |
Dan Gohman <gohman@apple.com> |
Split the SDValue out of OutputArg so that SelectionDAG-independent
code can do calling-convention queries. This obviates OutputArgReg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 1784d160e4efa75782884d451d0788b9457e67dc |
|
25-Jun-2010 |
Dale Johannesen <dalej@apple.com> |
The hasMemory argument is irrelevant to how the argument
for an "i" constraint should get lowered; PR 6309. While
this argument was passed around a lot, this is the only
place it was used, so it goes away from a lot of other
places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 022d9e1cef7586a80a96446ae8691a37def9bbf4 |
|
03-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Revert 95130.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 942619695f4bd77934c09a1cae0fb39ae59edac3 |
|
02-Feb-2010 |
Evan Cheng <evan.cheng@apple.com> |
Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 0c439eb2c8397996cbccaf2798e598052d9982c8 |
|
27-Jan-2010 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate target hook IsEligibleForTailCallOptimization.
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 65c3c8f323198b99b88b109654194540cf9b3fa5 |
|
02-Sep-2009 |
Sandeep Patel <deeppatel1987@gmail.com> |
Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| f1fa4fd282987381ab773d84a91e7de0cc4e5258 |
|
25-Aug-2009 |
Scott Michel <scottm@aero.org> |
128-bit sign extension and vector shift cleanups, contributed by Ken Werner
(IBM).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 77547befdc430633aaedf4130ddf17d953ed552e |
|
10-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Start moving TargetLowering away from using full MVTs and towards SimpleValueType, which will simplify the privatization of IntegerType in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 98ca4f2a325f72374a477f9deba7d09e8999c29b |
|
05-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 667ee3cb436029e55cc788a3648ddd9f94678744 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Small cleanups in the PowerPC backend.
Small refactoring in LowerFORMAL_ARGUMENTS().
Correct minor formatting issues.
Remove size argument of CreateCopyOfByValArgument().
Remove dead argument from CalculateStackSlotSize().
Remove unused variable ReturnAddrIndex from various targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| b4202b84d7e54efe5e144885c7da63e6cc465f80 |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Update comments to make it clear that the function alignment is the Log2 of the
bytes and not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 20c568f366be211323eeaf0e45ef053278ec9ddc |
|
01-Jul-2009 |
Bill Wendling <isanbard@gmail.com> |
Add an "alignment" field to the MachineFunction object. It makes more sense to
have the alignment be calculated up front, and have the back-ends obey whatever
alignment is decided upon.
This allows for future work that would allow for precise no-op placement and the
like.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 7ea02ffe918baff29a39981276e83b0e845ede03 |
|
17-Mar-2009 |
Scott Michel <scottm@aero.org> |
CellSPU:
- Fix fabs, fneg for f32 and f64.
- Use BuildVectorSDNode.isConstantSplat, now that the functionality exists
- Continue to improve i64 constant lowering. Lower certain special constants
to the constant pool when they correspond to SPU's shufb instruction's
special mask values. This avoids the overhead of performing a shuffle on a
zero-filled vector just to get the special constant when the memory load
suffices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| c9c8b2a804b2cd3d33a6a965e06a21ff93968f97 |
|
26-Jan-2009 |
Scott Michel <scottm@aero.org> |
CellSPU:
- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll
- Fix select_bits.ll test
- Capitulate to the DAGCombiner and move i64 constant loads to instruction
selection (SPUISelDAGtoDAG.cpp).
<rant>DAGCombiner will insert all kinds of 64-bit optimizations after
operation legalization occurs and now we have to do most of the work that
instruction selection should be doing twice (once to determine if v2i64
build_vector can be handled by SelectCode(), which then runs all of the
predicates a second time to select the necessary instructions.) But,
CellSPU is a good citizen.</rant>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| d1e8d9c0a5dc821b6b52f7872181edeeec5df7ba |
|
21-Jan-2009 |
Scott Michel <scottm@aero.org> |
CellSPU:
- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
Discovered interesting DAGCombiner feature, which is currently solved via
custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
insists on inserting one anyway.)
- Update README.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 94bd57e154088f2d45c465e73f896f64f6da4ade |
|
15-Jan-2009 |
Scott Michel <scottm@aero.org> |
- Convert remaining i64 custom lowering into custom instruction emission
sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom
DAG node types as needed.
- i64 mul is now a legal instruction, but emits an instruction sequence
that stretches tblgen and the imagination, as well as violating laws of
several small countries and most southern US states (just kidding, but
looking at a function with 80+ parameters is really weird and just plain
wrong.)
- Update tests as needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 21213e75b57f87182cbfa7cd8f55a37bcb7c4097 |
|
07-Jan-2009 |
Scott Michel <scottm@aero.org> |
CellSPU:
- Add preliminary support for v2i32; load/store generates the right code but
there's a lot work to be done to make this vector type operational.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 5480c0469e5c0323ffb12f1ead2abd169d6cc0e7 |
|
01-Jan-2009 |
Duncan Sands <baldrick@free.fr> |
Fix PR3274: when promoting the condition of a BRCOND node,
promote from i1 all the way up to the canonical SetCC type.
In order to discover an appropriate type to use, pass
MVT::Other to getSetCCResultType. In order to be able to
do this, change getSetCCResultType to take a type as an
argument, not a value (this is also more logical).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 02d711b93e3e0d2f0dae278360abe35305913e23 |
|
31-Dec-2008 |
Scott Michel <scottm@aero.org> |
- Start moving target-dependent nodes that could be represented by an
instruction sequence and cannot ordinarily be simplified by DAGcombine
into the various target description files or SPUDAGToDAGISel.cpp.
This makes some 64-bit operations legal.
- Eliminate target-dependent ISD enums.
- Update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
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| f0569be4a948c7ed816bfa2b8774a5a18458ee23 |
|
27-Dec-2008 |
Scott Michel <scottm@aero.org> |
- Remove Tilmann's custom truncate lowering: it completely hosed over
DAGcombine's ability to find reasons to remove truncates when they were not
needed. Consequently, the CellSPU backend would produce correct, but _really
slow and horrible_, code.
Replaced with instruction sequences that do the equivalent truncation in
SPUInstrInfo.td.
- Re-examine how unaligned loads and stores work. Generated unaligned
load code has been tested on the CellSPU hardware; see the i32operations.c
and i64operations.c in CodeGen/CellSPU/useful-harnesses. (While they may be
toy test code, it does prove that some real world code does compile
correctly.)
- Fix truncating stores in bug 3193 (note: unpack_df.ll will still make llc
fault because i64 ult is not yet implemented.)
- Added i64 eq and neq for setcc and select/setcc; started new instruction
information file for them in SPU64InstrInfo.td. Additional i64 operations
should be added to this file and not to SPUInstrInfo.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 30ee7df71c4b08da5d7e3f772f29f7c9ca57d8fa |
|
04-Dec-2008 |
Scott Michel <scottm@aero.org> |
CellSPU:
- First patch from Nehal Desai, a new contributor at Aerospace. Nehal's patch
fixes sign/zero/any-extending loads for integers and floating point. Example
code, compiled w/o debugging or optimization where he first noticed the bug:
int main(void) {
float a = 99.0;
printf("%d\n", a);
return 0;
}
Verified that this code actually works on a Cell SPU.
Changes by Scott Michel:
- Fix bug in the value type list constructed by SPUISD::LDRESULT to include
both the load result's result and chain, not just the chain alone.
- Simplify LowerLOAD and remove extraneous and unnecessary chains.
- Remove unused SPUISD pseudo instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 1607f05cb7d77d01ce521a30232faa389dbed4e2 |
|
01-Dec-2008 |
Duncan Sands <baldrick@free.fr> |
Change the interface to the type legalization method
ReplaceNodeResults: rather than returning a node which
must have the same number of results as the original
node (which means mucking around with MERGE_VALUES,
and which is also easy to get wrong since SelectionDAG
folding may mean you don't get the node you expect),
return the results in a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 104de4390b9bb0030ae81408c3d173ed6053378d |
|
24-Nov-2008 |
Scott Michel <scottm@aero.org> |
CellSPU:
(a) Improve the extract element code: there's no need to do gymnastics with
rotates into the preferred slot if a shuffle will do the same thing.
(b) Rename a couple of SPUISD pseudo-instructions for readability and better
semantic correspondence.
(c) Fix i64 sign/any/zero extension lowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 7a1c9e9cb7822afcf86b6575a3187974beecd9c6 |
|
23-Nov-2008 |
Scott Michel <scottm@aero.org> |
CellSPU: Fix bug 3056. Varadic extract_element was not implemented (nor was it
ever conceived to occur).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 73ce1c513fd7cb8afcb4215d8e96c1e6f02bfd34 |
|
11-Nov-2008 |
Scott Michel <scottm@aero.org> |
CellSPU: Fix bug 3606, as well as some ongoing work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 6520e20e4fb31f2e65e25c38b372b19d33a83df4 |
|
18-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| da43bcf624acb56a3d77bb5ae9a02728af032613 |
|
24-Sep-2008 |
Evan Cheng <evan.cheng@apple.com> |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 0ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bdd |
|
23-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Fix these enums' starting values to reflect the way that
instruction opcodes are now numbered. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 8bf61e8c2a39bcf070c39848fea83eda57851ebb |
|
03-Jun-2008 |
Scott Michel <scottm@aero.org> |
Add necessary 64-bit support so that gcc frontend compiles (mostly). Current
issue is operand promotion for setcc/select... but looks like the fundamental
stuff is implemented for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 203b2d6eed0f35fc8492c78ed2ae1afa854bfbf1 |
|
30-Apr-2008 |
Scott Michel <scottm@aero.org> |
Bug fixes and updates for CellSPU, syncing up with trunk. Most notable
fixes are target-specific lowering of frame indices, fix constants generated
for the FSMBI instruction, and fixing SPUTargetLowering::computeMaskedBitsFor-
TargetNode().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50462 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 2ba1c06d485949d01054cada0fef1fa5be27608a |
|
27-Apr-2008 |
Chris Lattner <sabre@nondot.org> |
no need to implement this method and just have it call
the default impl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 78c47fa50b903d5dcb4e07a5c048a35cbc2add9e |
|
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Integer comparison tests for CellSPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 5b8f82e35b51bf007de07a7ca9347d804084ddf8 |
|
10-Mar-2008 |
Scott Michel <scottm@aero.org> |
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48145 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| a59d469e9b31087f0f045bcb5d1a154c963be9b7 |
|
23-Feb-2008 |
Scott Michel <scottm@aero.org> |
Merge current work back to tree to minimize diffs and drift. Major highlights
for CellSPU modifications:
- SPUInstrInfo.td refactoring: "multiclass" really is _your_ friend.
- Other improvements based on refactoring effort in SPUISelLowering.cpp,
esp. in SPUISelLowering::PerformDAGCombine(), where zero amount shifts and
rotates are now eliminiated, other scalar-to-vector-to-scalar silliness
is also eliminated.
- 64-bit operations are being implemented, _muldi3.c gcc runtime now
compiles and generates the right code. More work still needs to be done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| ccef580583ad131fa42e5063536509de8158b0ba |
|
14-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
Fix single precision FP constants on SPU. They are actually legal,
which allows us to kill a target-specific node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3 |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
to pass the mask APInt by value, not by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47096 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| fd29e0eb060ea8b4d490860329234d2ae5f5952e |
|
13-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| ff9b373e8f5006c629af81e2619778b4c4f5249e |
|
30-Jan-2008 |
Evan Cheng <evan.cheng@apple.com> |
Even though InsertAtEndOfBasicBlock is an ugly hack it still deserves a proper name. Rename it to EmitInstrWithCustomInserter since it does not necessarily insert
instruction at the end.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 7f9ba9bb3c969eab32118dd21f15b4b74843c5c1 |
|
30-Jan-2008 |
Scott Michel <scottm@aero.org> |
More cleanups for CellSPU:
- Expand tabs... (poss 80-col violations, will get them later...)
- Consolidate logic for SelectDFormAddr and SelectDForm2Addr into a single
function, simplifying maintenance. Also reduced custom instruction
generation for SPUvecinsert/INSERT_MASK.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46544 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 053c1da8d956a794d158ac906b3927c923f97c4d |
|
29-Jan-2008 |
Scott Michel <scottm@aero.org> |
Overhaul Cell SPU's addressing mode internals so that there are now
only two addressing mode nodes, SPUaform and SPUindirect (vice the
three previous ones, SPUaform, SPUdform and SPUxform). This improves
code somewhat because we now avoid using reg+reg addressing when
it can be avoided. It also simplifies the address selection logic,
which was the main point for doing this.
Also, for various global variables that would be loaded using SPU's
A-form addressing, prefer D-form offs[reg] addressing, keeping the
base in a register if the variable is used more than once.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46483 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 9de5d0dd42463f61c4ee2f9db5f3d08153c0dacf |
|
11-Jan-2008 |
Scott Michel <scottm@aero.org> |
More CellSPU refinement and progress:
- Cleaned up custom load/store logic, common code is now shared [see note
below], cleaned up address modes
- More test cases: various intrinsics, structure element access (load/store
test), updated target data strings, indirect function calls.
Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode
structures: they now share a common base class, LSBaseSDNode, that
provides an interface to their common functionality. There is some hackery
to access the proper operand depending on the derived class; otherwise,
to do a proper job would require finding and rearranging the SDOperands
sent to StoreSDNode's constructor. The current refactor errs on the
side of being conservatively and backwardly compatible while providing
functionality that reduces redundant code for targets where loads and
stores are custom-lowered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 2466c3766dee7e65793bded413d02834dbc75629 |
|
05-Dec-2007 |
Scott Michel <scottm@aero.org> |
Updated source file headers to llvm coding standard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|
| 266bc8f7774b153401e54ed537db299159840981 |
|
04-Dec-2007 |
Scott Michel <scottm@aero.org> |
More of the Cell SPU code drop from "Team Aerospace".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/CellSPU/SPUISelLowering.h
|