| 97a454317af1903b269d42d368d2263ab79b6ed1 |
|
27-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
instructions.
- However, it does support dmb, dsb, isb, mrs, and msr.
rdar://11331541
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155685 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| e67a4163f5d2ad8e42a3aa0ccdaa27d85f6d5be4 |
|
26-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.
rdar://11318438
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 17463b3ef1a3d39b10619254f12e806c8c43f9e7 |
|
02-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| fd03ccddedce13a216c9b6e04e9d0ca6b163170e |
|
08-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM don't use MCRelaxAll, as it's not safe on ARM.
The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.
rdar://11006355
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| c6449b636f4984be88f128d0375c056ad05e7e8f |
|
05-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
Make MCRegisterInfo available to the the MCInstPrinter.
Used to allow context sensitive printing of super-register or sub-register
references.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| b0934ab7d811e23bf530371976b8b35f3242169c |
|
19-Feb-2012 |
Ahmed Charles <ace2001ac@gmail.com> |
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| f06dfa786064edc3bb6de92bb3783d0c23f4d34a |
|
10-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
Revert r150222, as the clang driver now handles this properly.
Now that the clang driver passes the CPU and feature information to
the backend when processing assembly files (150273), this isn't necessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| e009860049c0062fc1c708e46c7d868a84e3a41f |
|
10-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM on darwin, v6 implies the presence of VFP for the assembler.
rdar://10838899
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 |
|
16-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 928698b14e4bcd0f231dc28e246920a242d81fc1 |
|
18-Oct-2011 |
David Meyer <pdox@google.com> |
Remove NaClMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 6f09fcf5dae14d68ec9f8731b8c91c04868532e2 |
|
30-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Darwin default relocation model is PIC.
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| acad68da50581de905a994ed3c6b9c197bcea687 |
|
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 21a05e7017fa4056f3241f9c31afa4664c389c8e |
|
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARMv7a has the PKH instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| b950585cc5a0d665e9accfe5ce490cd269756f2e |
|
07-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 1fac6b50ea720d75fc2bf01a288e99f239869e90 |
|
05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 7442a03dcc2ac7850a77ec7c639973d8dc6034ae |
|
05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Fix typo in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3 |
|
24-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move TargetRegistry and TargetSelect from Target to Support where they belong.
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 7801136b95d1fbe515b9655b73ada39b05a33559 |
|
23-Aug-2011 |
Evan Cheng <evan.cheng@apple.com> |
Some refactoring so TargetRegistry.h no longer has to include any files
from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 9bd7c2836eea4ba6484a1eabb38cd084f45fed94 |
|
09-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 41ab14b725c8f2bb3e54553d0d7d96ff184786b1 |
|
08-Aug-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 28c85a81a17dd719a254dc00cbeb484774893197 |
|
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to createMCObjectStreamer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136031 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 78c10eeaa57d1c6c4b7781d3c0bcb0cfbbc43b5c |
|
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 4b64e8a9e13ba782da2034e1dee52f077bdb759c |
|
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Separate MCInstPrinter registration from AsmPrinter registration.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| be74029f44c32efc09274a16cbff588ad10dc5ea |
|
23-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink ARM mc routines into MCTargetDesc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135825 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| e78085a3c03de648a481e9751c3094c517bd7123 |
|
22-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,
InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 34ad6db8b958fdc0d38e122edf753b5326e69b03 |
|
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
code model for JIT. This eliminates the ugly hack in TargetMachine where
code model is changed after construction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| e76a33b9567d78a5744dc52fcec3a6056d6fb576 |
|
20-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.
TargetAsmInfo is done to one last method. It's *almost* gone!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 439661395fd2a2a832dba01c65bc88718528313c |
|
19-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Introduce MCCodeGenInfo, which keeps information that can affect codegen
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 0e6a052331f674dd70e28af41f654a7874405eab |
|
18-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.
This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 1be0e271a07925b928ba89848934f1ea6f1854e2 |
|
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatest
solution but it is a small step towards removing the horror that is
TargetAsmInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 1abf2cb59b8d63415780a03329307c0997b2670c |
|
15-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename createAsmInfo to createMCAsmInfo and move registration code to MCTargetDesc to prepare for next round of changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
|
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| ffc0e73046f737d75e0a62b3a83ef19bcef111e3 |
|
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| ebdeeab812beec0385b445f3d4c41a114e0d972f |
|
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 963b03c1a9f6a9742671459f103ee9a566c6de58 |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename attribute 'thumb' to a more descriptive 'thumb-mode'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| db068738e806753bc5735434cab9b9f930840c7a |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink feature IsThumb into MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 94ca42ff0407d71bacc41de4032d8dbe6358d33d |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|
| 78a9f138ae95458bf6d922f38706eed045691d5a |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM MC registry routines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
|