1//===-- ARMMCTargetDesc.cpp - ARM Target Descriptions ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file provides ARM specific target descriptions.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMMCTargetDesc.h"
15#include "ARMMCAsmInfo.h"
16#include "ARMBaseInfo.h"
17#include "InstPrinter/ARMInstPrinter.h"
18#include "llvm/MC/MCCodeGenInfo.h"
19#include "llvm/MC/MCInstrAnalysis.h"
20#include "llvm/MC/MCInstrInfo.h"
21#include "llvm/MC/MCRegisterInfo.h"
22#include "llvm/MC/MCStreamer.h"
23#include "llvm/MC/MCSubtargetInfo.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/TargetRegistry.h"
26
27#define GET_REGINFO_MC_DESC
28#include "ARMGenRegisterInfo.inc"
29
30#define GET_INSTRINFO_MC_DESC
31#include "ARMGenInstrInfo.inc"
32
33#define GET_SUBTARGETINFO_MC_DESC
34#include "ARMGenSubtargetInfo.inc"
35
36using namespace llvm;
37
38std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
39  // Set the boolean corresponding to the current target triple, or the default
40  // if one cannot be determined, to true.
41  unsigned Len = TT.size();
42  unsigned Idx = 0;
43
44  // FIXME: Enhance Triple helper class to extract ARM version.
45  bool isThumb = false;
46  if (Len >= 5 && TT.substr(0, 4) == "armv")
47    Idx = 4;
48  else if (Len >= 6 && TT.substr(0, 5) == "thumb") {
49    isThumb = true;
50    if (Len >= 7 && TT[5] == 'v')
51      Idx = 6;
52  }
53
54  bool NoCPU = CPU == "generic" || CPU.empty();
55  std::string ARMArchFeature;
56  if (Idx) {
57    unsigned SubVer = TT[Idx];
58    if (SubVer >= '7' && SubVer <= '9') {
59      if (Len >= Idx+2 && TT[Idx+1] == 'm') {
60        if (NoCPU)
61          // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
62          ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
63        else
64          // Use CPU to figure out the exact features.
65          ARMArchFeature = "+v7";
66      } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
67        if (NoCPU)
68          // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2,
69          //       FeatureT2XtPk, FeatureMClass
70          ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass";
71        else
72          // Use CPU to figure out the exact features.
73          ARMArchFeature = "+v7";
74      } else {
75        // v7 CPUs have lots of different feature sets. If no CPU is specified,
76        // then assume v7a (e.g. cortex-a8) feature set. Otherwise, return
77        // the "minimum" feature set and use CPU string to figure out the exact
78        // features.
79        if (NoCPU)
80          // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk
81          ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk";
82        else
83          // Use CPU to figure out the exact features.
84          ARMArchFeature = "+v7";
85      }
86    } else if (SubVer == '6') {
87      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
88        ARMArchFeature = "+v6t2";
89      else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
90        if (NoCPU)
91          // v6m: FeatureNoARM, FeatureMClass
92          ARMArchFeature = "+v6,+noarm,+mclass";
93        else
94          ARMArchFeature = "+v6";
95      } else
96        ARMArchFeature = "+v6";
97    } else if (SubVer == '5') {
98      if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e')
99        ARMArchFeature = "+v5te";
100      else
101        ARMArchFeature = "+v5t";
102    } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't')
103      ARMArchFeature = "+v4t";
104  }
105
106  if (isThumb) {
107    if (ARMArchFeature.empty())
108      ARMArchFeature = "+thumb-mode";
109    else
110      ARMArchFeature += ",+thumb-mode";
111  }
112
113  return ARMArchFeature;
114}
115
116MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU,
117                                                  StringRef FS) {
118  std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
119  if (!FS.empty()) {
120    if (!ArchFS.empty())
121      ArchFS = ArchFS + "," + FS.str();
122    else
123      ArchFS = FS;
124  }
125
126  MCSubtargetInfo *X = new MCSubtargetInfo();
127  InitARMMCSubtargetInfo(X, TT, CPU, ArchFS);
128  return X;
129}
130
131static MCInstrInfo *createARMMCInstrInfo() {
132  MCInstrInfo *X = new MCInstrInfo();
133  InitARMMCInstrInfo(X);
134  return X;
135}
136
137static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
138  MCRegisterInfo *X = new MCRegisterInfo();
139  InitARMMCRegisterInfo(X, ARM::LR);
140  return X;
141}
142
143static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) {
144  Triple TheTriple(TT);
145
146  if (TheTriple.isOSDarwin())
147    return new ARMMCAsmInfoDarwin();
148
149  return new ARMELFMCAsmInfo();
150}
151
152static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM,
153                                             CodeModel::Model CM,
154                                             CodeGenOpt::Level OL) {
155  MCCodeGenInfo *X = new MCCodeGenInfo();
156  if (RM == Reloc::Default) {
157    Triple TheTriple(TT);
158    // Default relocation model on Darwin is PIC, not DynamicNoPIC.
159    RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC;
160  }
161  X->InitMCCodeGenInfo(RM, CM, OL);
162  return X;
163}
164
165// This is duplicated code. Refactor this.
166static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
167                                    MCContext &Ctx, MCAsmBackend &MAB,
168                                    raw_ostream &OS,
169                                    MCCodeEmitter *Emitter,
170                                    bool RelaxAll,
171                                    bool NoExecStack) {
172  Triple TheTriple(TT);
173
174  if (TheTriple.isOSDarwin())
175    return createMachOStreamer(Ctx, MAB, OS, Emitter, false);
176
177  if (TheTriple.isOSWindows()) {
178    llvm_unreachable("ARM does not support Windows COFF format");
179  }
180
181  return createELFStreamer(Ctx, MAB, OS, Emitter, false, NoExecStack);
182}
183
184static MCInstPrinter *createARMMCInstPrinter(const Target &T,
185                                             unsigned SyntaxVariant,
186                                             const MCAsmInfo &MAI,
187                                             const MCInstrInfo &MII,
188                                             const MCRegisterInfo &MRI,
189                                             const MCSubtargetInfo &STI) {
190  if (SyntaxVariant == 0)
191    return new ARMInstPrinter(MAI, MII, MRI, STI);
192  return 0;
193}
194
195namespace {
196
197class ARMMCInstrAnalysis : public MCInstrAnalysis {
198public:
199  ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
200
201  virtual bool isUnconditionalBranch(const MCInst &Inst) const {
202    // BCCs with the "always" predicate are unconditional branches.
203    if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
204      return true;
205    return MCInstrAnalysis::isUnconditionalBranch(Inst);
206  }
207
208  virtual bool isConditionalBranch(const MCInst &Inst) const {
209    // BCCs with the "always" predicate are unconditional branches.
210    if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
211      return false;
212    return MCInstrAnalysis::isConditionalBranch(Inst);
213  }
214
215  uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr,
216                          uint64_t Size) const {
217    // We only handle PCRel branches for now.
218    if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
219      return -1ULL;
220
221    int64_t Imm = Inst.getOperand(0).getImm();
222    // FIXME: This is not right for thumb.
223    return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes.
224  }
225};
226
227}
228
229static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
230  return new ARMMCInstrAnalysis(Info);
231}
232
233// Force static initialization.
234extern "C" void LLVMInitializeARMTargetMC() {
235  // Register the MC asm info.
236  RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo);
237  RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo);
238
239  // Register the MC codegen info.
240  TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo);
241  TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo);
242
243  // Register the MC instruction info.
244  TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
245  TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
246
247  // Register the MC register info.
248  TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
249  TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
250
251  // Register the MC subtarget info.
252  TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
253                                          ARM_MC::createARMMCSubtargetInfo);
254  TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
255                                          ARM_MC::createARMMCSubtargetInfo);
256
257  // Register the MC instruction analyzer.
258  TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget,
259                                          createARMMCInstrAnalysis);
260  TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget,
261                                          createARMMCInstrAnalysis);
262
263  // Register the MC Code Emitter
264  TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter);
265  TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter);
266
267  // Register the asm backend.
268  TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend);
269  TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend);
270
271  // Register the object streamer.
272  TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer);
273  TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer);
274
275  // Register the MCInstPrinter.
276  TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
277  TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);
278}
279