/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 19 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, argument 30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); 45 MachineInstr *DefMI = LastMI; local 55 DefMI = &*I; 59 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && 61 hasRAWHazard(DefMI, MI, TRI))) {
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H A D | MLxExpansionPass.cpp | 92 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 94 if (DefMI->getParent() != MBB) 96 if (DefMI->isCopyLike()) { 97 Reg = DefMI->getOperand(1).getReg(); 99 DefMI = MRI->getVRegDef(Reg); 102 } else if (DefMI->isInsertSubreg()) { 103 Reg = DefMI->getOperand(2).getReg(); 105 DefMI = MRI->getVRegDef(Reg); 111 return DefMI; 160 MachineInstr *DefMI [all...] |
H A D | ARMExpandPseudoInsts.cpp | 55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 74 MachineInstrBuilder &DefMI) { 83 DefMI.addOperand(MO); 72 TransferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI) argument
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H A D | ARMBaseInstrInfo.cpp | 1646 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this); local 1647 bool Invert = !DefMI; 1648 if (!DefMI) 1649 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this); 1650 if (!DefMI) 1653 // Create a new predicated version of DefMI. 1656 DefMI->getDesc(), 1659 // Copy all the DefMI operands, excluding its (null) predicate. 1660 const MCInstrDesc &DefDesc = DefMI->getDesc(); 1663 NewMI.addOperand(DefMI 2229 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument 2763 adjustDefLatency(const ARMSubtarget &Subtarget, const MachineInstr *DefMI, const MCInstrDesc *DefMCID, unsigned DefAlign) argument 2913 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3189 getOutputLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const argument 3269 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 3292 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LiveRangeEdit.cpp | 46 const MachineInstr *DefMI, 48 assert(DefMI && "Missing instruction"); 50 if (!TII.isTriviallyReMaterializable(DefMI, aa)) 62 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); local 63 if (!DefMI) 65 checkRematerializable(VNI, DefMI, aa); 155 MachineInstr *DefMI = 0, *UseMI = 0; local 163 if (DefMI && DefMI != MI) 167 DefMI 45 checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI, AliasAnalysis *aa) argument [all...] |
H A D | PHIElimination.cpp | 138 MachineInstr *DefMI = *I; local 139 unsigned DefReg = DefMI->getOperand(0).getReg(); 141 DefMI->eraseFromParent(); 327 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) 328 if (DefMI->isImplicitDef()) 329 ImpDefs.insert(DefMI);
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H A D | PeepholeOptimizer.cpp | 332 MachineInstr *DefMI = MRI->getVRegDef(Src); local 333 if (!DefMI || !DefMI->isBitcast()) 337 NumDefs = DefMI->getDesc().getNumDefs(); 338 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; 342 const MachineOperand &MO = DefMI->getOperand(i); 540 MachineInstr *DefMI = 0; local 542 FoldAsLoadDefReg, DefMI); 544 // Update LocalMIs since we replaced MI with FoldMI and deleted DefMI. 546 LocalMIs.erase(DefMI); [all...] |
H A D | EarlyIfConversion.cpp | 244 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 245 if (!DefMI || DefMI->getParent() != Head) 247 if (InsertAfter.insert(DefMI)) 248 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " depends on " << *DefMI); 249 if (DefMI->isTerminator()) {
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H A D | MachineCSE.cpp | 131 MachineInstr *DefMI = MRI->getVRegDef(Reg); local 132 if (DefMI->getParent() != MBB) 134 if (!DefMI->isCopy()) 136 unsigned SrcReg = DefMI->getOperand(1).getReg(); 139 if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg()) 143 DEBUG(dbgs() << "Coalescing: " << *DefMI); 147 DefMI->eraseFromParent();
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H A D | StrongPHIElimination.cpp | 253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); local 254 if (DefMI) 255 PHISrcDefs[DefMI->getParent()].push_back(DefMI);
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H A D | TailDuplication.cpp | 236 MachineInstr *DefMI = MRI->getVRegDef(VReg); local 238 if (DefMI) { 239 DefBB = DefMI->getParent();
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H A D | TargetInstrInfoImpl.cpp | 565 const MachineInstr *DefMI) const { 566 if (DefMI->mayLoad()) 568 if (isHighLatencyDef(DefMI->getOpcode())) 586 const MachineInstr *DefMI, 591 unsigned DefClass = DefMI->getDesc().getSchedClass(); 596 /// Both DefMI and UseMI must be valid. By default, call directly to the 600 const MachineInstr *DefMI, unsigned DefIdx, 602 unsigned DefClass = DefMI->getDesc().getSchedClass(); 611 const MachineInstr *DefMI, bool FindMin) { 615 return TII->getInstrLatency(ItinData, DefMI); 585 hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const argument 599 getOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument 609 computeDefOperandLatency( const TargetInstrInfo *TII, const InstrItineraryData *ItinData, const MachineInstr *DefMI, bool FindMin) argument 650 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx, bool FindMin) const argument [all...] |
H A D | InlineSpiller.cpp | 108 MachineInstr *DefMI; member in struct:__anon8665::InlineSpiller::SibValueInfo 119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 122 bool hasDef() const { return DefByOrigPHI || DefMI; } 329 if (SVI.DefMI) 330 OS << " def: " << *SVI.DefMI; 393 DepSV.DefMI = SV.DefMI; 482 return SVI->second.DefMI; 600 SVI->second.DefMI = MI; 621 return SVI->second.DefMI; 644 MachineInstr *DefMI = 0; local 719 MachineInstr *DefMI = LIS.getInstructionFromIndex(SVI.SpillVNI->def); local [all...] |
H A D | LiveIntervalAnalysis.cpp | 193 MachineInstr *DefMI = getInstructionFromIndex(OldLR->valno->def); local 194 if (DefMI != 0) { 195 return DefMI->findRegisterDefOperandIdx(interval.reg) != -1;
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H A D | TwoAddressInstructionPass.cpp | 369 MachineInstr *DefMI = &MI; local 371 if (!DefMI->killsRegister(Reg)) 380 DefMI = &*Begin; 385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 860 MachineInstr *DefMI = &*DI; local 861 if (DefMI->getParent() != MBB || DefMI->isCopy() || DefMI->isCopyLike()) 863 if (DefMI == MI) 865 DenseMap<MachineInstr*, unsigned>::iterator DDI = DistanceMap.find(DefMI); 1686 MachineInstr *DefMI = NULL; local [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 746 /// defined by the load we are trying to fold. DefMI returns the machine 752 MachineInstr *&DefMI) const { 758 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, argument 791 const MachineInstr *DefMI, unsigned DefIdx, 800 const MachineInstr *DefMI, unsigned DefIdx, 808 const MachineInstr *DefMI, unsigned DefIdx, 825 const MachineInstr *DefMI) const; 839 const MachineInstr *DefMI, unsigned DefIdx, 848 const MachineInstr *DefMI, unsigned DefIdx) const = 0; 1022 const MachineInstr *DefMI, unsigne 807 getOutputLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *DepMI) const argument 837 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.cpp | 1507 MachineInstr *DefMI = I.getOperand().getParent(); local 1508 if (DefMI->getOpcode() != X86::MOVPC32r) 3395 MachineInstr *&DefMI) const { 3404 // Check whether we can move DefMI here. 3405 DefMI = MRI->getVRegDef(FoldAsLoadDefReg); 3406 assert(DefMI); 3408 if (!DefMI->isSafeToMove(this, 0, SawStore)) 3436 MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI); 4626 const MachineInstr *DefMI, unsigned DefIdx, 4628 return isHighLatencyDef(DefMI 4624 hasHighOperandLatency(const InstrItineraryData *ItinData, const MachineRegisterInfo *MRI, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx) const argument [all...] |