Searched defs:MI1 (Results 1 - 3 of 3) sorted by relevance

/external/llvm/lib/CodeGen/
H A DTargetInstrInfoImpl.cpp235 const MachineInstr *MI1,
237 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
234 produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const argument
/external/llvm/lib/Target/Hexagon/
H A DHexagonVLIWPacketizer.cpp141 bool ArePredicatesComplements(MachineInstr* MI1, MachineInstr* MI2,
3084 bool HexagonPacketizerList::ArePredicatesComplements (MachineInstr* MI1, argument
3089 if (!QII->isConditionalTransfer(MI1) || !QII->isConditionalTransfer(MI2)) {
3094 SUnit* SU = MIToSUnit[MI1];
3153 return ((MI1->getOperand(1).getReg() == MI2->getOperand(1).getReg()) &&
3154 (GetPredicateSense(MI1, QII) != GetPredicateSense(MI2, QII)) &&
3155 (isDotNewInst(MI1) == isDotNewInst(MI2)));
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp1263 const MachineInstr *MI1,
1275 if (MI1->getOpcode() != Opcode)
1277 if (MI0->getNumOperands() != MI1->getNumOperands())
1281 const MachineOperand &MO1 = MI1->getOperand(1);
1312 if (MI1->getOpcode() != Opcode)
1314 if (MI0->getNumOperands() != MI1->getNumOperands())
1318 unsigned Addr1 = MI1->getOperand(1).getReg();
1337 const MachineOperand &MO1 = MI1->getOperand(i);
1344 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1262 produceSameValue(const MachineInstr *MI0, const MachineInstr *MI1, const MachineRegisterInfo *MRI) const argument

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