Searched defs:NumVecs (Results 1 - 2 of 2) sorted by relevance
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 203 /// SelectVLD - Select NEON load intrinsics. NumVecs should be 206 /// For NumVecs <= 2, QOpcodes1 is not used. 207 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, 211 /// SelectVST - Select NEON store intrinsics. NumVecs should 214 /// For NumVecs <= 2, QOpcodes1 is not used. 215 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, 219 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should 223 bool isUpdating, unsigned NumVecs, 226 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs 229 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, 1526 GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector) argument 1591 SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument 1724 SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes0, const uint16_t *QOpcodes1) argument 1870 SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, unsigned NumVecs, const uint16_t *DOpcodes, const uint16_t *QOpcodes) argument 1990 SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs, const uint16_t *Opcodes) argument 2074 SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc) argument [all...] |
H A D | ARMISelLowering.cpp | 8201 unsigned NumVecs = 0; local 8207 NumVecs = 1; break; 8209 NumVecs = 2; break; 8211 NumVecs = 3; break; 8213 NumVecs = 4; break; 8215 NumVecs = 2; isLaneOp = true; break; 8217 NumVecs = 3; isLaneOp = true; break; 8219 NumVecs = 4; isLaneOp = true; break; 8221 NumVecs = 1; isLoad = false; break; 8223 NumVecs 8318 unsigned NumVecs = 0; local [all...] |
Completed in 68 milliseconds