Searched defs:UseIdx (Results 1 - 7 of 7) sorted by relevance

/external/llvm/lib/CodeGen/
H A DLiveRangeEdit.cpp77 /// OrigIdx are also available with the same value at UseIdx.
80 SlotIndex UseIdx) {
82 UseIdx = UseIdx.getRegSlot(true);
99 if (OVNI != li.getVNInfoAt(UseIdx))
106 SlotIndex UseIdx,
129 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx))
78 allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx, SlotIndex UseIdx) argument
105 canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove) argument
H A DTargetInstrInfoImpl.cpp518 SDNode *UseNode, unsigned UseIdx) const {
529 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
601 const MachineInstr *UseMI, unsigned UseIdx) const {
604 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
648 /// UseIdx to compute min latency.
652 const MachineInstr *UseMI, unsigned UseIdx,
663 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
650 computeOperandLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx, const MachineInstr *UseMI, unsigned UseIdx, bool FindMin) const argument
H A DInlineSpiller.cpp835 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); local
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
845 DEBUG(dbgs() << UseIdx << '\t' << *MI);
857 if (!Edit->canRematerializeAt(RM, UseIdx, false)) {
859 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI);
870 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI);
901 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI);
904 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI));
H A DMachineVerifier.cpp978 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); local
983 LiveRangeQuery LRQ(*LI, UseIdx);
986 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI)
1001 LiveRangeQuery LRQ(LI, UseIdx);
1004 *OS << UseIdx << " is not live in " << LI << '\n';
H A DRegisterCoalescer.cpp600 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); local
601 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
652 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); local
653 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx);
672 SlotIndex DefIdx = UseIdx.getRegSlot();
H A DSplitKit.cpp430 SlotIndex UseIdx,
443 if (Edit->canRematerializeAt(RM, UseIdx, true)) {
428 defFromParent(unsigned RegIdx, VNInfo *ParentVNI, SlotIndex UseIdx, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) argument
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2530 unsigned UseIdx, unsigned UseAlign) const {
2531 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2533 return ItinData->getOperandCycle(UseClass, UseIdx);
2570 unsigned UseIdx, unsigned UseAlign) const {
2571 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
2573 return ItinData->getOperandCycle(UseClass, UseIdx);
2600 unsigned UseIdx, unsigned UseAlign) const {
2604 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
2605 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
2655 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
2527 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
2567 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument
2596 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument
2731 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument
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