Searched defs:V2 (Results 26 - 50 of 61) sorted by relevance

123

/external/clang/test/CodeGenCXX/
H A Dvtable-layout.cpp203 struct V2 : virtual V1 { int v1; }; struct in namespace:Test4
214 // CHECK-9-NEXT: 2 | Test4::V2 *Test4::D::f()
216 // CHECK-9-NEXT: 3 | Test4::V2 *Test4::D::f()
218 virtual V2 *f();
220 V2 *D::f() { return 0; };
947 struct V2 : virtual V1 { struct in namespace:Test22
961 // CHECK-29-NEXT: -- (Test22::V2, 16) vtable address --
963 // CHECK-29: Construction vtable for ('Test22::V2', 16) in 'Test22::C' (3 entries).
966 // CHECK-29-NEXT: 2 | Test22::V2 RTTI
968 struct C : virtual V1, virtual V2 {
1327 struct V2 : virtual V1 { }; struct in namespace:Test29
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/external/llvm/include/llvm/Analysis/
H A DAliasAnalysis.h176 const Value *V2, uint64_t V2Size) {
177 return alias(Location(V1, V1Size), Location(V2, V2Size));
181 AliasResult alias(const Value *V1, const Value *V2) { argument
182 return alias(V1, UnknownSize, V2, UnknownSize);
193 const Value *V2, uint64_t V2Size) {
194 return isNoAlias(Location(V1, V1Size), Location(V2, V2Size));
198 bool isNoAlias(const Value *V1, const Value *V2) { argument
199 return isNoAlias(Location(V1), Location(V2));
208 bool isMustAlias(const Value *V1, const Value *V2) { argument
209 return alias(V1, 1, V2,
175 alias(const Value *V1, uint64_t V1Size, const Value *V2, uint64_t V2Size) argument
192 isNoAlias(const Value *V1, uint64_t V1Size, const Value *V2, uint64_t V2Size) argument
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/external/llvm/include/llvm/Support/
H A DNoFolder.h280 Instruction *CreateShuffleVector(Constant *V1, Constant *V2, argument
282 return new ShuffleVectorInst(V1, V2, Mask);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXUtilities.cpp369 const Value *V2 = V->stripPointerCasts(); local
370 if (V2 != V && processed.find(V2) != processed.end())
372 processed.insert(V2);
374 V = V2;
386 if (V != V2 && processed.find(V) != processed.end())
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineLoadStoreAlloca.cpp426 // load (select (Cond, &V1, &V2)) --> select(Cond, load &V1, load &V2).
432 LoadInst *V2 = Builder->CreateLoad(SI->getOperand(2), local
435 V2->setAlignment(Align);
436 return SelectInst::Create(SI->getCondition(), V1, V2);
H A DInstCombineShifts.cpp406 Value *V1, *V2; local
465 m_And(m_Shr(m_Value(V1), m_Value(V2)),
466 m_ConstantInt(CC))) && V2 == Op1 &&
H A DInstCombineAndOrXor.cpp1804 Value *V1 = 0, *V2 = 0; local
1813 match(A, m_Add(m_Value(V1), m_Value(V2)))) {
1815 if (V1 == B && MaskedValueIsZero(V2, C2->getValue()))
1817 if (V2 == B && MaskedValueIsZero(V1, C2->getValue()))
1822 match(B, m_Add(m_Value(V1), m_Value(V2)))) {
1824 if (V1 == A && MaskedValueIsZero(V2, C1->getValue()))
1826 if (V2 == A && MaskedValueIsZero(V1, C1->getValue()))
1834 if (match(A, m_Or(m_Value(V1), m_Value(V2))) &&
1835 ((V1 == B && MaskedValueIsZero(V2, ~C1->getValue())) || // (V|N)
1836 (V2
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H A DInstCombineCasts.cpp1416 Value *V2; local
1421 V2 = UndefValue::get(SrcTy);
1429 V2 = Constant::getNullValue(SrcTy);
1439 return new ShuffleVectorInst(InVal, V2,
1440 ConstantDataVector::get(V2->getContext(),
/external/clang/lib/StaticAnalyzer/Core/
H A DExprEngineC.cpp849 DefinedSVal V2 = cast<DefinedSVal>(V2_untested); local
866 SVal Result = evalBinOp(state, Op, V2, RHS, U->getType());
879 svalBuilder.evalEQ(state, V2,svalBuilder.makeZeroVal(U->getType()));
899 state = state->BindExpr(U, LCtx, U->isPostfix() ? V2 : Result);
H A DExprEngine.cpp1322 llvm::APSInt V2; local
1324 V2 = E->EvaluateKnownConstInt(getContext());
1326 V2 = V1;
1362 if (V1 == V2)
1366 assert (V1 <= V2);
/external/llvm/include/llvm/
H A DInstrTypes.h178 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
180 return Create(Instruction::OPC, V1, V2, Name);\
184 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
186 return Create(Instruction::OPC, V1, V2, Name, BB);\
190 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
192 return Create(Instruction::OPC, V1, V2, Name, I);\
196 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
198 BinaryOperator *BO = Create(Opc, V1, V2, Name);
202 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, argument
204 BinaryOperator *BO = Create(Opc, V1, V2, Nam
208 CreateNSW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
215 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = Ó) argument
221 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
227 CreateNUW(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
234 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name = Ó) argument
240 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, BasicBlock *BB) argument
246 CreateExact(BinaryOps Opc, Value *V1, Value *V2, const Twine &Name, Instruction *I) argument
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H A DIRBuilder.h1229 Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask, argument
1232 if (Constant *V2C = dyn_cast<Constant>(V2))
1235 return Insert(new ShuffleVectorInst(V1, V2, Mask), Name);
/external/llvm/lib/CodeGen/
H A DMachineModuleInfo.cpp50 virtual void allUsesReplacedWith(Value *V2);
247 void MMIAddrLabelMapCallbackPtr::allUsesReplacedWith(Value *V2) { argument
248 Map->UpdateForRAUWBlock(cast<BasicBlock>(getValPtr()), cast<BasicBlock>(V2));
/external/llvm/lib/Target/Mips/
H A DMipsISelDAGToDAG.cpp128 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); local
140 V2 = RegInfo.createVirtualRegister(RC);
164 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
166 .addReg(V1).addReg(V2);
/external/llvm/lib/Transforms/IPO/
H A DMergeFunctions.cpp172 bool enumerate(const Value *V1, const Value *V2);
377 bool FunctionComparator::enumerate(const Value *V1, const Value *V2) { argument
381 if (V1 == F1 && V2 == F2)
383 if (V1 == F2 && V2 == F1)
387 if (V1 == V2) return true;
388 const Constant *C2 = dyn_cast<Constant>(V2);
400 if (isa<InlineAsm>(V1) || isa<InlineAsm>(V2))
401 return V1 == V2;
403 // Check that V1 maps to V2. If we find a value that V1 maps to then we simply
404 // check whether it's equal to V2
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/external/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp955 Value *V2 = EmitAddTreeOfValues(I, Ops); local
956 return BinaryOperator::CreateAdd(V2, V1, "tmp", I);
1251 Instruction *V2 = BinaryOperator::CreateMul(V, MaxOccVal, "tmp", I);
1255 RedoInsts.insert(V2);
1260 return V2;
1265 Ops.insert(Ops.begin(), ValueEntry(getRank(V2), V2));
H A DCodeGenPrepare.cpp349 const Value *V2 = PN->getIncomingValueForBlock(BB); local
351 // If V2 is a phi node in BB, look up what the mapped value will be.
352 if (const PHINode *V2PN = dyn_cast<PHINode>(V2))
354 V2 = V2PN->getIncomingValueForBlock(Pred);
357 if (V1 != V2) return false;
/external/llvm/lib/Analysis/
H A DBasicAliasAnalysis.cpp503 const Value *V2, uint64_t V2Size,
511 const Value *V2, uint64_t V2Size,
517 const Value *V2, uint64_t V2Size,
522 const Value *V2, uint64_t V2Size,
837 /// anything about V2. UnderlyingV1 is GetUnderlyingObject(GEP1, TD),
838 /// UnderlyingV2 is the same for V2.
843 const Value *V2, uint64_t V2Size,
853 if (const GEPOperator *GEP2 = dyn_cast<GEPOperator>(V2)) {
927 V2, V2Size, V2TBAAInfo);
929 // If V2 ma
841 aliasGEP(const GEPOperator *GEP1, uint64_t V1Size, const MDNode *V1TBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo, const Value *UnderlyingV1, const Value *UnderlyingV2) argument
1020 aliasSelect(const SelectInst *SI, uint64_t SISize, const MDNode *SITBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo) argument
1054 aliasPHI(const PHINode *PN, uint64_t PNSize, const MDNode *PNTBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo) argument
1156 aliasCheck(const Value *V1, uint64_t V1Size, const MDNode *V1TBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo) argument
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/external/llvm/lib/VMCore/
H A DConstantFold.cpp693 Constant *V1, Constant *V2) {
695 if (Cond->isNullValue()) return V2;
706 Constant *V = Cond->isNullValue() ? V2 : V1;
718 return V2;
720 if (isa<UndefValue>(V1)) return V2;
721 if (isa<UndefValue>(V2)) return V1;
722 if (V1 == V2) return V1;
727 return ConstantExpr::getSelect(Cond, TrueVal->getOperand(1), V2);
729 if (ConstantExpr *FalseVal = dyn_cast<ConstantExpr>(V2)) {
782 Constant *V2,
692 ConstantFoldSelectInstruction(Constant *Cond, Constant *V1, Constant *V2) argument
781 ConstantFoldShuffleVectorInstruction(Constant *V1, Constant *V2, Constant *Mask) argument
1272 evaluateFCmpRelation(Constant *V1, Constant *V2) argument
1340 evaluateICmpRelation(Constant *V1, Constant *V2, bool isSigned) argument
1647 APInt V2 = cast<ConstantInt>(C2)->getValue(); local
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H A DConstants.cpp1725 Constant *ConstantExpr::getSelect(Constant *C, Constant *V1, Constant *V2) { argument
1726 assert(!SelectInst::areInvalidOperands(C, V1, V2)&&"Invalid select operands");
1728 if (Constant *SC = ConstantFoldSelectInstruction(C, V1, V2))
1733 argVec[2] = V2;
1853 Constant *ConstantExpr::getShuffleVector(Constant *V1, Constant *V2, argument
1855 assert(ShuffleVectorInst::isValidOperands(V1, V2, Mask) &&
1858 if (Constant *FC = ConstantFoldShuffleVectorInstruction(V1, V2, Mask))
1867 ArgVec.push_back(V2);
/external/opencv/cvaux/src/
H A Dcveigenobjects.cpp87 float *A2 = A + n * (p + 1), *V2 = V + n * (p + 1); local
89 for( q = p + 1; q < n; q++, A2 += n, V2 += n )
119 Vqi = V2[i];
123 V2[i] = (float) (Vqi * c + Vpi * s);
130 Vqi = V2[i];
134 V2[i] = (float) (Vqi * c + Vpi * s);
141 Vqi = V2[i];
145 V2[i] = (float) (Vqi * c + Vpi * s);
/external/clang/lib/CodeGen/
H A DCGValue.h42 llvm::PointerIntPair<llvm::Value *, 1, bool> V2; member in class:clang::CodeGen::RValue
49 bool isVolatileQualified() const { return V2.getInt(); }
60 return std::make_pair(V1.getPointer(), V2.getPointer());
73 ER.V2.setInt(false);
76 static RValue getComplex(llvm::Value *V1, llvm::Value *V2) { argument
79 ER.V2.setPointer(V2);
81 ER.V2.setInt(false);
94 ER.V2.setInt(Volatile);
/external/llvm/lib/Target/ARM/
H A DARMCodeEmitter.cpp779 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); local
811 Binary |= getMachineSoImmOpValue(V2);
H A DARMISelDAGToDAG.cpp274 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1480 SDValue V2, SDValue V3) {
1489 V2, SubReg2, V3, SubReg3 };
1496 SDValue V2, SDValue V3) {
1504 V2, SubReg2, V3, SubReg3 };
1511 SDValue V2, SDValue V3) {
1519 V2, SubReg2, V3, SubReg3 };
1785 SDValue V2 local
1479 QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1495 QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1510 QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3) argument
1835 SDValue V2 = N->getOperand(Vec0Idx + 2); local
1953 SDValue V2 = N->getOperand(Vec0Idx + 2); local
2088 SDValue V2 = N->getOperand(FirstTblReg + 2); local
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/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.cpp1824 /// LowerVECTOR_SHUFFLE - Lower a vector shuffle (V1, V2, V3) to something on
1830 /// permute/shuffle the bytes from V1 and V2.
1834 /// element move from V2 into V1.
1840 SDValue V2 = Op.getOperand(1); local
1843 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1845 // If we have a single element being moved from V1 to V2, this can be handled
1886 // elements are taken form V2. Do we ever get such a case?
1931 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
1953 return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMas
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