Searched refs:i1 (Results 226 - 250 of 283) sorted by relevance

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/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
/external/openssh/
H A Dssh-keygen.c390 int magic, rlen, ktype, i1, i2, i3, i4; local
403 i1 = buffer_get_int(&b);
409 debug("ignore (%d %d %d %d)", i1, i2, i3, i4);
/external/guava/guava-tests/test/com/google/common/collect/
H A DIterablesTest.java1173 Iterator<String> i1 = Iterables.consumingIterable(list).iterator();
1176 i1.next();
H A DIteratorsTest.java1490 Iterator<String> i1 = Iterators.consumingIterator(list.iterator());
1493 i1.next();
/external/icu4c/test/cintltst/
H A Dcitertst.c917 static void assertEqual(UCollationElements *i1, UCollationElements *i2) argument
925 c1 = ucol_next(i1, &status);
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp703 // Sparc doesn't have i1 sign extending load
704 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
716 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
/external/elfutils/tests/
H A Drun-allregs.sh2381 25: %i1 (i1), signed 32 bits
2459 25: %i1 (i1), signed 64 bits
/external/llvm/unittests/ADT/
H A DAPIntTest.cpp107 TEST(APIntTest, i1) {
/external/opencv/cv/src/
H A Dcvfilter.cpp255 int i1, i2, di; local
261 i1 = border_tab_sz1 - pix_sz;
268 i1 = border_tab_sz1;
279 for( i = i1; i != i2; i += di )
/external/clang/lib/Sema/
H A DSemaDeclObjC.cpp2516 for (AttrVec::const_iterator i1 = D.begin(), e1 = D.end(); i1 != e1; ++i1) {
2517 if ((*i)->getKind() == (*i1)->getKind()) {
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp103 // Mips does not have i1 type, so use i32 for
131 // Load extented operations for i1 types must be promoted
132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
/external/v8/src/
H A Djsregexp.cc4543 int i1 = 0; local
4554 while (i1 < n1 || i2 < n2) {
4558 (i1 < n1 && first_set->at(i1).from() < second_set->at(i2).from())) {
4560 next_range = first_set->at(i1++);
H A Dprofile-generator.cc3196 static int Intersect(int i1, int i2, const Vector<int>& dominators) { argument
3197 int finger1 = i1, finger2 = i2;
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
201 // We cannot sextinreg(i1). Expand to shifts.
202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
236 setOperationAction(ISD::VAARG, MVT::i1, Promote);
237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp1517 // add (sext i1), X -> sub X, (zext i1)
1519 N0.getOperand(0).getValueType() == MVT::i1 &&
1520 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) {
3391 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
4053 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
4057 (VT0 == MVT::i1 ||
4073 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
4079 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
4085 if (VT == MVT::i1
[all...]
H A DSelectionDAGBuilder.cpp302 // Handle cases such as i8 -> <1 x i1>
700 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
702 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
1582 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
1594 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
1599 Cond = DAG.getSetCC(dl, MVT::i1, SUB,
1963 SDValue Cond = DAG.getSetCC(DL, MVT::i1,
5196 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
5567 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp580 // ARM does not have i1 sign extending load.
581 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
587 setIndexedLoadAction(im, MVT::i1, Legal);
591 setIndexedStoreAction(im, MVT::i1, Legal);
725 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
7032 // Detects these expressions where cc is an i1 value:
7073 if (CC.getValueType() != MVT::i1)
7101 // Also recognize sext/zext from i1:
8950 DAG.getValueType(MVT::i1));
9086 case MVT::i1
[all...]
/external/chromium/third_party/libjingle/source/talk/session/phone/testdata/
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1436 �� hea(G ��\�����m�%�[�_���:'�I��=>�q��:�6И޵�ۡO���3P�з��3�߻�𵩂 $v5�HQ|9���)���U�� ��T&1�7��Hz�����E��}�_��W�G���pǽ�߱�3߸�m��w���@�“�4s�1�hs��7xߪ�g9�c�^�b�ӯ�W~�X���w��:��������������JI�b][��C4o��z^����/����!B�]��?�!�o�+S��f߿���'z��� ���eܪK��+�~׸{���`GL���]���@�b?Q�_��ov���k⸓�41�A�%�X7����Q�0՚8$t>L>�����&���ӗ�_���ӯ �m6�����}���~�w+ǹY�/������W�Uv�0fǚn�\�?����{~m���=&30�CM5���<M�/��+���_@?��#}��㻴���o��k��ҿ�Mr��E��/q�������e^P�w�Re��5c����-�o��z���Z��6��F�Q����c#wrj����.���f���fuQ#�g#��B���_�|p�L�k\%��c�Y����ג���^���k��;^�غ�Eк�g�w����n^�{������Ju=���}�)���������n����{߀��N��>`n�&��.��f�O�r�!�xb�'��{�� B�Ai1�:���<w/�._��+�2h���?��Ʃ�������_��ˢl_c�8Nb�L��07�r�������<^7�%"��~Di��LtcK&�����fb�Ц���6a�^!�����`��&���:��M��/"qVnLo�i�������#�P����Ɏ?n��و��,f7b�����v~��0�@`X]��>an�2���.��f��r�!�d' ��W��a�Ŀ��_��ᐦu�_|׏&/w���Z�ֿ�Bw��
/external/qemu/block/
H A Dvvfat.c2095 int i1 = array_index(&(s->mapping), mapping); local
2100 i1++;
2101 mapping = array_get(&(s->mapping), i1);
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/
H A Dorg.mortbay.jetty.server_6.1.23.v201004211559.jarMETA-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ...
H A Dorg.eclipse.equinox.p2.publisher_1.1.2.v20100824-2220.jarMETA-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ...
/external/valgrind/main/VEX/priv/
H A Dhost_s390_defs.c452 genSpill_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument
460 *i1 = *i2 = NULL;
467 *i1 = s390_insn_store(8, am, rreg);
479 genReload_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument
487 *i1 = *i2 = NULL;
494 *i1 = s390_insn_load(8, rreg, am);
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
378 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
441 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
1644 if (Subtarget->is64Bit() && VT == MVT::i1
[all...]
/external/llvm/lib/Target/CellSPU/
H A DSPUISelDAGToDAG.cpp82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
/external/opencv/ml/src/
H A Dmltree.cpp1686 int i1 = cvRandInt(r) % n;
1688 CV_SWAP( labels[i1], labels[i2], j );

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