/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
|
/external/openssh/ |
H A D | ssh-keygen.c | 390 int magic, rlen, ktype, i1, i2, i3, i4; local 403 i1 = buffer_get_int(&b); 409 debug("ignore (%d %d %d %d)", i1, i2, i3, i4);
|
/external/guava/guava-tests/test/com/google/common/collect/ |
H A D | IterablesTest.java | 1173 Iterator<String> i1 = Iterables.consumingIterable(list).iterator(); 1176 i1.next();
|
H A D | IteratorsTest.java | 1490 Iterator<String> i1 = Iterators.consumingIterator(list.iterator()); 1493 i1.next();
|
/external/icu4c/test/cintltst/ |
H A D | citertst.c | 917 static void assertEqual(UCollationElements *i1, UCollationElements *i2) argument 925 c1 = ucol_next(i1, &status);
|
/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 703 // Sparc doesn't have i1 sign extending load 704 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 716 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
|
/external/elfutils/tests/ |
H A D | run-allregs.sh | 2381 25: %i1 (i1), signed 32 bits 2459 25: %i1 (i1), signed 64 bits
|
/external/llvm/unittests/ADT/ |
H A D | APIntTest.cpp | 107 TEST(APIntTest, i1) {
|
/external/opencv/cv/src/ |
H A D | cvfilter.cpp | 255 int i1, i2, di; local 261 i1 = border_tab_sz1 - pix_sz; 268 i1 = border_tab_sz1; 279 for( i = i1; i != i2; i += di )
|
/external/clang/lib/Sema/ |
H A D | SemaDeclObjC.cpp | 2516 for (AttrVec::const_iterator i1 = D.begin(), e1 = D.end(); i1 != e1; ++i1) { 2517 if ((*i)->getKind() == (*i1)->getKind()) {
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 103 // Mips does not have i1 type, so use i32 for 131 // Load extented operations for i1 types must be promoted 132 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 133 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 134 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 144 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
|
/external/v8/src/ |
H A D | jsregexp.cc | 4543 int i1 = 0; local 4554 while (i1 < n1 || i2 < n2) { 4558 (i1 < n1 && first_set->at(i1).from() < second_set->at(i2).from())) { 4560 next_range = first_set->at(i1++);
|
H A D | profile-generator.cc | 3196 static int Intersect(int i1, int i2, const Vector<int>& dominators) { argument 3197 int finger1 = i1, finger2 = i2;
|
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD 88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); 99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); 201 // We cannot sextinreg(i1). Expand to shifts. 202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 236 setOperationAction(ISD::VAARG, MVT::i1, Promote); 237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | DAGCombiner.cpp | 1517 // add (sext i1), X -> sub X, (zext i1) 1519 N0.getOperand(0).getValueType() == MVT::i1 && 1520 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 3391 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 4053 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4057 (VT0 == MVT::i1 || 4073 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4079 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4085 if (VT == MVT::i1 [all...] |
H A D | SelectionDAGBuilder.cpp | 302 // Handle cases such as i8 -> <1 x i1> 700 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 702 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 1582 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1594 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1599 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1963 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 5196 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 5567 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal,
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 580 // ARM does not have i1 sign extending load. 581 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 587 setIndexedLoadAction(im, MVT::i1, Legal); 591 setIndexedStoreAction(im, MVT::i1, Legal); 725 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 7032 // Detects these expressions where cc is an i1 value: 7073 if (CC.getValueType() != MVT::i1) 7101 // Also recognize sext/zext from i1: 8950 DAG.getValueType(MVT::i1)); 9086 case MVT::i1 [all...] |
/external/chromium/third_party/libjingle/source/talk/session/phone/testdata/ |
H A D | video.rtpdump | 141 J'ꋿ���I�O��㒱�Q^�5�X�&t(�C���}25@��x7���Z�Ԙ-�seG��m05�"�ǎ�\������>+),K�_��?��֬��7��3�)��Ys|'��B�Õ����]�[�#۳n1��#_~�0��� ^J� ���6�/Y%x�+
)���u�YױDr���Da��j�� ���=�n~�
��.�� f ���r !��b.a;�u�����v5��XG���3369W'(��{�&d?=qZ��{u���bd_�̌&E�'��x�o7�]k ̨L��3�L �\��%?��D4'�/��ֲ�C��Bჯ�m��L���Kc��;n��BZ%C��A67����B,�h��y���(L������
����M�$��|��(����(On�3q-}�Gg�o���|��-�Bge�cMq&�����C�ggo�p��!���Lg* ŸFaFyb6��*ӱt*��.�)��1{���ǚ:���71/��i����1�{���������a���`���Y&)��F!��X���%����Q�Q�g=b��1|��'_��� ���=�n~�O��.�� f ����r !��f2�i1�d%�]���� �?���¿(��Mrp��tHm����?t���J�O*�$���d@���)�/�K.x��A�#1D���W �N:��i�/9��'���oC�����~���#�����a�̊:�ƶ[��=��/��k'���7B�ظ��|��|�z�|'_�u��L��c�I����4� 418 �i1�oNUP>Gw�zLl�F�P�϶��������3��h� 614 �>Fw��H���Bhi��>2�-����p�|������1�W"�`W�o%����x�����?w�� ���>����݃�i1�sS�p��@� Í �g��E�e����>5�L���/b��( ���=�n�V'��.�� f ��u8r b!�d!��v4�c1?���J��#N���Oa�k���@t.�|wN�:u͞��C< ��β�yF A�x� �ŝ��0�ؾa�-X���sX��qf� 9�.�T̿���BE���|�}�?����y3\�_s�)�ɋ���X�{�u9r����l�]+�R��-3B�>�S����d��ɵ����>�A�Z���`������o�;�����L�������?��)���#q��b�|%� � �'�u����_����\ޯ��&8c';9���A'�����b��h 929 "����I��+k3_���!�@�
����V��Y�.q8>^錦c�J3���hVu3��+C����1�"3�_�++�?�pX;�D�^�L�����pv�C; ��>n�p�.�� f �ߚ�r �!�X-���H��8&�v��_��7p�=�ͪՎ����-1:��S8�&1���3�<��ت�O�2�X[h(��,hx�>�F�_�t�Q�͊E�J���+ߕM�+���b�%T�O~�4/�`m���i1��N{���Xa���X��ֽ~�O���&���1_w̾#����-z�HE ���^:��= �r������ҭD�:�N���Z�>�A�����ό�7�R)z�߲���%u��v>"p7|Vݾߋ�e%������&�9�`l��[�#�" ��?�D�WO ���>n�}f��.�� f ���r �!�xv0b��}���@ĉ����L�S/eW�D1X�V(F �]���Ne
ؙ��y�F�|��J�c�x����e�^�S#������{+��"@�&+sr����!��\���2���/����O��S�y1?lj2���PX����+>Vl[�3��'���>w���Ҷ�܋�1:���Pui�ɫ�Z0���VҶ�����&OW_$K� �^(D��_��o4����E �]HP�t�o��O`���W'��۷����]�¶��{&��;��Q���f�y�~]K�#�V%�#��zb�
B�\�� ��>n�����.�� f ��.sr �!�=���7�����hT+�0��L/hT�D/YB$��,H�X�]U~$B 1071 Zh�O}��}g�����V`:NLk6������]r�7�N+˾�7/�fw��'_�.$Go����sf��,x薁�'�/�f(�.�]ra��1]cpǐG^��|�8F������%ro�ך*C�&�i1\M��\�:t�A��꼘��4��Q8�$F�����r!<�W��#���3�g?��%�Gh�G�=���K�?�Jv~u�`��j�6��y'hX�Ys螪�W���Ƚ3�����0��+��
�E<L�O@Z �wL��gS1 ��B�F�aY ��>)n��ꗃ.�� f �� 1436 ��hea(G
��\�����m�%�[�_���:'�I��=>�q��:�6И�ۡO���3P�з��3��
$v5�HQ|9���)���U�� ��T&1�7��Hz�����E��}�_��W�G���pǽ�߱�3 ߸�m��w���@��4s�1�hs��7xߪ�g9 �c�^�b�ӯ�W~�X���w��:��������������JI�b][��C4o��z^� ���/����!B�]��?�!�o�+S��f߿���'z������eܪK��+�~{���`GL���]���@�b?Q�_��ov���k⸓�41�A�%�X7����Q�0՚8$t>L>�����&���ӗ�_���ӯ �m6�����}���~�w+ǹY�/������W�Uv�0fǚn�\�?����{~m���=&30�CM5���<M�/��+���_@?��#}��㻴���o��k��ҿ�Mr��E��/q�������e^P�w�Re��5c����-�o��z���Z��6��F�Q����c#wrj����.���f���fuQ#�g#��B���_�|p�L�k\%��c�Y����ג���^���k��;^�غ�Eк�g�w����n^�{������Ju=���}�)���������n����{߀ � � N��>`n�&��.�� f �O�r �!�xb�'��{��
B�Ai1�:���<w/�._��+�2h���?��Ʃ�������_��ˢl_c�8Nb�L��07�r�������<^7�%"��~Di��LtcK&�����fb�Ц���6a�^!�����`��&���:��M��/"qVnLo�i�������#�P����Ɏ?n��و��,f7b�����v~��0�@`X ]��>an�2���.�� f ��r �!�d'��W��a�Ŀ��_��ᐦu�_|&/w���Z�ֿ�Bw��
|
/external/qemu/block/ |
H A D | vvfat.c | 2095 int i1 = array_index(&(s->mapping), mapping); local 2100 i1++; 2101 mapping = array_get(&(s->mapping), i1);
|
/external/eclipse-basebuilder/basebuilder-3.6.2/org.eclipse.releng.basebuilder/plugins/ |
H A D | org.mortbay.jetty.server_6.1.23.v201004211559.jar | META-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ... |
H A D | org.eclipse.equinox.p2.publisher_1.1.2.v20100824-2220.jar | META-INF/MANIFEST.MF META-INF/ECLIPSEF.SF META-INF/ECLIPSEF.RSA META ... |
/external/valgrind/main/VEX/priv/ |
H A D | host_s390_defs.c | 452 genSpill_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument 460 *i1 = *i2 = NULL; 467 *i1 = s390_insn_store(8, am, rreg); 479 genReload_S390(HInstr **i1, HInstr **i2, HReg rreg, Int offsetB, Bool mode64) argument 487 *i1 = *i2 = NULL; 494 *i1 = s390_insn_load(8, rreg, am);
|
/external/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 230 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 250 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 266 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 268 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 291 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 293 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 307 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 378 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 441 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 1644 if (Subtarget->is64Bit() && VT == MVT::i1 [all...] |
/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 82 if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
|
/external/opencv/ml/src/ |
H A D | mltree.cpp | 1686 int i1 = cvRandInt(r) % n; 1688 CV_SWAP( labels[i1], labels[i2], j );
|