/external/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.h | 31 /// DstReg - The register that will be left after coalescing. It can be a 33 unsigned DstReg; member in class:llvm::CoalescerPair 38 /// DstIdx - The sub-register index of the old DstReg in the new coalesced 52 /// Flipped - True when DstReg and SrcReg are reversed from the original 56 /// NewRC - The register class of the coalesced register, or NULL if DstReg 58 /// SrcReg and DstReg. 63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), 70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), 77 /// flip - Swap SrcReg and DstReg. Return false if swapping is impossible 78 /// because DstReg i [all...] |
H A D | ExpandPostRAPseudos.cpp | 52 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg, 64 /// TransferDeadFlag - MI is a pseudo-instruction with DstReg dead, 68 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg, argument 72 if (MII->addRegisterDead(DstReg, TRI)) 102 unsigned DstReg = MI->getOperand(0).getReg(); local 108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 110 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && 122 if (DstReg != InsReg) { 134 // Implicitly define DstReg for subsequent uses. 137 CopyMI->addRegisterDefined(DstReg); [all...] |
H A D | OptimizePHIs.cpp | 87 unsigned DstReg = MI->getOperand(0).getReg(); local 100 if (SrcReg == DstReg) 130 unsigned DstReg = MI->getOperand(0).getReg(); local 131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && 142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg),
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H A D | TwoAddressInstructionPass.cpp | 134 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB, 145 void CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg); 333 unsigned &SrcReg, unsigned &DstReg, 336 DstReg = 0; 338 DstReg = MI.getOperand(0).getReg(); 341 DstReg = MI.getOperand(0).getReg(); 347 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); 382 unsigned SrcReg, DstReg; local 385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) 393 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { argument 332 isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII, unsigned &SrcReg, unsigned &DstReg, bool &IsSrcPhys, bool &IsDstPhys) argument 413 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument 634 ScanUses(unsigned DstReg, MachineBasicBlock *MBB, SmallPtrSet<MachineInstr*, 8> &Processed) argument 698 unsigned SrcReg, DstReg; local 746 unsigned DstReg; local 901 unsigned DstReg; local 1215 unsigned DstReg = DstMO.getReg(); local 1427 unsigned DstReg = mi->getOperand(DstIdx).getReg(); local 1475 UpdateRegSequenceSrcs(unsigned SrcReg, unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI, const TargetRegisterInfo &TRI) argument 1527 CoalesceExtSubRegs(SmallVector<unsigned,4> &Srcs, unsigned DstReg) argument 1663 unsigned DstReg = MI->getOperand(0).getReg(); local [all...] |
H A D | PeepholeOptimizer.cpp | 144 unsigned SrcReg, DstReg, SubIdx; local 145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 148 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || 156 // Ensure DstReg can get a register class that actually supports 158 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); 175 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); 258 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); 271 // About to add uses of DstReg, clear DstReg's kill flags. 273 MRI->clearKillFlags(DstReg); [all...] |
H A D | RegisterCoalescer.cpp | 113 /// joinCopy - Attempt to join intervals corresponding to SrcReg/DstReg, 148 bool reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg, 154 /// updateRegDefsUses - Replace all defs and uses of SrcReg to DstReg and 155 /// update the subregister number if it is not zero. If DstReg is a 159 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx); 222 SrcReg = DstReg = 0; 275 // SrcReg will be merged with a sub-register of DstReg. 279 // DstReg will be merged with a sub-register of SrcReg. 291 // Prefer SrcReg to be a sub-register of DstReg. 306 DstReg 703 reMaterializeTrivialDef(LiveInterval &SrcInt, unsigned DstReg, MachineInstr *CopyMI) argument 843 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument [all...] |
H A D | EarlyIfConversion.cpp | 112 // Latencies from Cond+Branch, TReg, and FReg to DstReg. 463 unsigned DstReg = PI.PHI->getOperand(0).getReg(); local 464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 484 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); local 485 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 488 // Rewrite PHI operands TPred -> (DstReg, Head), remove FPred. 493 PI.PHI->getOperand(i-2).setReg(DstReg);
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H A D | MachineSink.cpp | 130 unsigned DstReg = MI->getOperand(0).getReg(); local 132 !TargetRegisterInfo::isVirtualRegister(DstReg) || 137 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 146 MRI->replaceRegWith(DstReg, SrcReg);
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H A D | LiveDebugVariables.cpp | 566 unsigned DstReg = MI->getOperand(0).getReg(); local 572 if (!TargetRegisterInfo::isVirtualRegister(DstReg)) 582 if (!LIS.hasInterval(DstReg)) 584 LiveInterval *DstLI = &LIS.getInterval(DstReg);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 133 unsigned DstReg = Dst.getReg(); local 136 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 141 PeepholeMap[DstReg] = SrcReg; 157 unsigned DstReg = Dst.getReg(); local 159 PeepholeDoubleRegsMap[DstReg] = 169 unsigned DstReg = Dst.getReg(); local 172 if (TargetRegisterInfo::isVirtualRegister(DstReg) && 177 PeepholeMap[DstReg] = SrcReg; 192 unsigned DstReg = Dst.getReg(); local 194 if (TargetRegisterInfo::isVirtualRegister(DstReg) [all...] |
H A D | HexagonExpandPredSpillCode.cpp | 122 // DstReg = LDriw_pred [R30], ofst. 123 int DstReg = MI->getOperand(0).getReg(); local 124 assert(Hexagon::PredRegsRegClass.contains(DstReg) && 145 DstReg).addReg(HEXAGON_RESERVED_REG_2); 154 DstReg).addReg(HEXAGON_RESERVED_REG_2); 160 DstReg).addReg(HEXAGON_RESERVED_REG_2);
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.h | 32 unsigned DstReg, int64_t Value, DebugLoc dl) const; 40 unsigned DstReg, int Offset, DebugLoc dl) const;
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H A D | XCoreRegisterInfo.cpp | 303 unsigned DstReg, int64_t Value, DebugLoc dl) const { 310 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value); 302 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int64_t Value, DebugLoc dl) const argument
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H A D | XCoreFrameLowering.cpp | 47 unsigned DstReg, int Offset, DebugLoc dl, 55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) 45 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DstReg, int Offset, DebugLoc dl, const TargetInstrInfo &TII) argument
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 208 unsigned DstReg = MI.getOperand(0).getReg(); local 210 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 211 .addReg(DstReg).addImm(-Offset); 213 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) 214 .addReg(DstReg).addImm(Offset);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMExpandPseudoInsts.cpp | 388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); local 390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 516 unsigned DstReg = 0; 520 DstReg = MI.getOperand(OpIdx++).getReg(); 521 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 617 unsigned DstReg = MI.getOperand(0).getReg(); local 626 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 628 .addReg(DstReg, RegStat 867 unsigned DstReg = MI.getOperand(0).getReg(); local 891 unsigned DstReg = MI.getOperand(0).getReg(); local 951 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); local [all...] |
H A D | Thumb2ITBlockPass.cpp | 117 unsigned DstReg = MI->getOperand(0).getReg(); local 121 if (Uses.count(DstReg) || Defs.count(SrcReg))
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H A D | MLxExpansionPass.cpp | 209 unsigned DstReg = MI->getOperand(0).getReg(); local 235 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
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H A D | ARMBaseInstrInfo.cpp | 3400 unsigned DstReg, SrcReg, DReg; local 3416 DstReg = MI->getOperand(0).getReg(); 3424 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 3434 DstReg = MI->getOperand(0).getReg(); 3446 AddDefaultPred(MIB.addReg(DstReg, RegState::Define) 3460 DstReg = MI->getOperand(0).getReg(); 3463 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); 3486 MIB.addReg(DstReg, RegState::Define | RegState::Implicit); 3493 DstReg = MI->getOperand(0).getReg(); 3497 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLan [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 132 unsigned DstReg = MI->getOperand(0).getReg(); local 135 if (DstReg != SrcReg) 136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 144 if (DstReg != SrcReg) 145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 153 if (DstReg != SrcReg) 154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) [all...] |
H A D | PPCInstrInfo.h | 96 unsigned &SrcReg, unsigned &DstReg,
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelDAGToDAG.cpp | 225 unsigned DstReg = 0, ZeroReg = 0; local 231 DstReg = MI.getOperand(0).getReg(); 236 DstReg = MI.getOperand(0).getReg(); 240 if (!DstReg) 244 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
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H A D | MipsSEInstrInfo.cpp | 328 unsigned DstReg = I->getOperand(0).getReg(); local 338 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); 343 unsigned DstReg = I->getOperand(0).getReg(); 351 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven)) 353 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 168 unsigned &SrcReg, unsigned &DstReg, 227 unsigned DstReg,
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 114 unsigned &SrcReg, unsigned &DstReg, 393 /// copy TrueReg to DstReg when Cond is true, and FalseReg to DstReg when 404 /// @param DstReg Virtual register to be defined by select instruction. 410 unsigned DstReg, 113 isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SubIdx) const argument 408 insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned DstReg, const SmallVectorImpl<MachineOperand> &Cond, unsigned TrueReg, unsigned FalseReg) const argument
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