Searched refs:Ins (Results 1 - 25 of 42) sorted by relevance

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/external/llvm/lib/CodeGen/
H A DCallingConvLower.cpp67 CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, argument
69 unsigned NumArgs = Ins.size();
72 MVT ArgVT = Ins[i].VT;
73 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
155 void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
157 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
158 MVT VT = Ins[i].VT;
159 ISD::ArgFlagsTy Flags = Ins[i].Flags;
H A DRegAllocGreedy.cpp707 unsigned Ins = 0; local
712 BC.Entry = SpillPlacement::MustSpill, ++Ins; local
714 BC.Entry = SpillPlacement::PrefSpill, ++Ins; local
716 ++Ins;
722 BC.Exit = SpillPlacement::MustSpill, ++Ins; local
724 BC.Exit = SpillPlacement::PrefSpill, ++Ins; local
726 ++Ins;
730 if (Ins)
731 StaticCost += Ins * SpillPlacer->getBlockFrequency(BC.Number);
918 unsigned Ins
[all...]
/external/llvm/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp67 &Ins,
70 unsigned NumArgs = Ins.size();
81 EVT ArgVT = Ins[i].VT;
82 ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
180 Hexagon_CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, argument
184 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
185 EVT VT = Ins[i].VT;
66 AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, Hexagon_CCAssignFn Fn, unsigned SretValueInRegs) argument
H A DHexagonISelLowering.h79 const SmallVectorImpl<ISD::InputArg> &Ins,
94 const SmallVectorImpl<ISD::InputArg> &Ins,
104 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DHexagonCallingConvLower.h80 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
102 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h130 const SmallVectorImpl<ISD::InputArg> &Ins,
137 const SmallVectorImpl<ISD::InputArg> &Ins,
144 const SmallVectorImpl<ISD::InputArg> &Ins,
151 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMSP430ISelLowering.cpp249 &Ins,
260 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
262 if (Ins.empty())
275 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
291 Outs, OutVals, Ins, dl, DAG, InVals);
306 &Ins,
319 CCInfo.AnalyzeFormalArguments(Ins, CC_MSP430);
446 const SmallVectorImpl<ISD::InputArg> &Ins,
558 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, d
245 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
302 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
440 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
566 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Transforms/IPO/
H A DPartialInlining.cpp93 BasicBlock::iterator Ins = newReturnBlock->begin(); local
98 PHINode* retPhi = PHINode::Create(OldPhi->getType(), 2, "", Ins);
100 Ins = newReturnBlock->getFirstNonPHI();
H A DIPConstantPropagation.cpp250 Instruction *Ins = cast<Instruction>(*I); local
257 if (ExtractValueInst *EV = dyn_cast<ExtractValueInst>(Ins))
270 Ins->replaceAllUsesWith(New);
271 Ins->eraseFromParent();
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h387 const SmallVectorImpl<ISD::InputArg> &Ins,
431 const SmallVectorImpl<ISD::InputArg> &Ins,
442 const SmallVectorImpl<ISD::InputArg> &Ins,
448 const SmallVectorImpl<ISD::InputArg> &Ins,
472 const SmallVectorImpl<ISD::InputArg> &Ins,
478 const SmallVectorImpl<ISD::InputArg> &Ins,
487 const SmallVectorImpl<ISD::InputArg> &Ins,
495 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DPPCISelLowering.cpp1715 &Ins,
1720 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1723 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1733 &Ins,
1784 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1845 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1951 &Ins,
2004 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2006 EVT ObjectVT = Ins[ArgNo].VT;
2007 ISD::ArgFlagsTy Flags = Ins[ArgN
1712 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1729 LowerFormalArguments_SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1947 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2400 IsEligibleForTailCallOptimization(SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument
2812 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2838 FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall, bool isVarArg, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue InFlag, SDValue Chain, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) const argument
2951 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
2973 LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3186 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h114 const SmallVectorImpl<ISD::InputArg> &Ins,
122 const SmallVectorImpl<ISD::InputArg> &Ins,
127 const SmallVectorImpl<ISD::InputArg> &Ins,
172 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DXCoreISelLowering.cpp883 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
901 Outs, OutVals, Ins, dl, DAG, InVals);
915 const SmallVectorImpl<ISD::InputArg> &Ins,
1030 Ins, dl, DAG, InVals);
1038 const SmallVectorImpl<ISD::InputArg> &Ins,
1047 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1069 const SmallVectorImpl<ISD::InputArg> &Ins,
1081 Ins, dl, DAG, InVals);
1094 &Ins,
910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1036 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1066 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1090 LowerCCCArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
/external/llvm/lib/Target/MBlaze/
H A DMBlazeISelLowering.h115 const SmallVectorImpl<ISD::InputArg> &Ins,
130 const SmallVectorImpl<ISD::InputArg> &Ins,
H A DMBlazeISelLowering.cpp690 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
831 if (!Ins.empty())
837 Ins, dl, DAG, InVals);
844 bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins,
852 CCInfo.AnalyzeCallResult(Ins, RetCC_MBlaze);
874 const SmallVectorImpl<ISD::InputArg> &Ins,
895 CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze);
1000 // the size of Ins and InVals. This only happens when on varg functions
843 LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
873 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp448 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; local
605 if (Ins.size() > 0) {
699 DAG.getConstant(isABI ? ((Ins.size()==0) ? 0 : 1)
750 if (Ins.size() > 0) {
753 for (unsigned i=0,e=Ins.size(); i!=e; ++i) {
754 unsigned sz = Ins[i].VT.getSizeInBits();
755 if (Ins[i].VT.isInteger() && (sz < 8)) sz = 8;
757 LoadRetVTs.push_back(Ins[i].VT);
776 assert(Ins
913 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
[all...]
H A DNVPTXISelLowering.h104 const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl,
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h74 const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.h82 Ins, enumerator in enum:llvm::MipsISD::NodeType
128 const SmallVectorImpl<ISD::InputArg> &Ins,
158 const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h75 std::pair<CompMap::iterator, bool> Ins = local
77 return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second;
/external/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h196 void AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
223 void AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.h457 const SmallVectorImpl<ISD::InputArg> &Ins,
464 const SmallVectorImpl<ISD::InputArg> &Ins,
492 const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/lib/Target/CellSPU/
H A DSPUISelLowering.h156 const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h723 const SmallVectorImpl<ISD::InputArg> &Ins,
749 const SmallVectorImpl<ISD::InputArg> &Ins,
842 const SmallVectorImpl<ISD::InputArg> &Ins,
/external/llvm/include/llvm/Transforms/Utils/
H A DSSAUpdaterImpl.h71 SmallVectorImpl<PhiT*> *Ins) :
72 Updater(U), AvailableVals(A), InsertedPHIs(Ins) { }
70 SSAUpdaterImpl(UpdaterT *U, AvailableValsTy *A, SmallVectorImpl<PhiT*> *Ins) argument

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