Searched refs:RS (Results 1 - 25 of 77) sorted by relevance

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/external/clang/lib/StaticAnalyzer/Checkers/
H A DReturnUndefChecker.cpp30 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
34 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, argument
37 const Expr *RetE = RS->getRetValue();
H A DReturnPointerRangeChecker.cpp30 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
34 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, argument
38 const Expr *RetE = RS->getRetValue();
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h63 int SPAdj, RegScavenger *RS) const;
65 int SPAdj, RegScavenger *RS) const;
67 int SPAdj, RegScavenger *RS) const;
69 int SPAdj, RegScavenger *RS = NULL) const;
H A DPPCJITInfo.cpp27 #define BUILD_ADDIS(RD,RS,IMM16) \
28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
29 #define BUILD_ORI(RD,RS,UIMM16) \
30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
31 #define BUILD_ORIS(RD,RS,UIMM16) \
32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
33 #define BUILD_RLDICR(RD,RS,SH,ME) \
34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
36 #define BUILD_MTSPR(RS,SPR) \
37 ((31 << 26) | ((RS) << 2
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/external/qemu/
H A Dppc-dis.c84 /* Opcode is defined for the POWER (RS/6000) architecture. */
729 the RS field in the instruction. This is used for extended
734 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
737 #define RS RBS + 1
738 #define RT RS
742 /* The RS and RT fields of the DS form stq instruction, which have
744 #define RSQ RS + 1
748 /* The RS field of the tlbwe instruction, which is optional. */
1455 the RS field in the instruction. This is used for extended
2153 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, R
733 #define RS macro
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/external/llvm/lib/Target/CellSPU/
H A DSPUFrameLowering.h44 RegScavenger *RS = NULL) const;
H A DSPURegisterInfo.h80 RegScavenger *RS = NULL) const;
99 RegScavenger *RS,
H A DSPURegisterInfo.cpp256 RegScavenger *RS) const
300 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
347 RegScavenger *RS,
351 assert(RS && "Register scavenging must be on");
352 unsigned Reg = RS->FindUnusedReg(RC);
354 Reg = RS->scavengeRegister(RC, II, SPAdj);
346 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) const argument
/external/llvm/lib/Target/MBlaze/
H A DMBlazeFrameLowering.h47 RegScavenger *RS) const;
H A DMBlazeRegisterInfo.h59 int SPAdj, RegScavenger *RS = NULL) const;
/external/llvm/lib/Target/Mips/
H A DMips16FrameLowering.h38 RegScavenger *RS) const;
H A DMipsSEFrameLowering.h39 RegScavenger *RS) const;
H A DMipsRegisterInfo.h56 int SPAdj, RegScavenger *RS = NULL) const;
H A DMips16FrameLowering.cpp81 RegScavenger *RS) const {
/external/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.h44 int SPAdj, RegScavenger *RS = NULL) const;
/external/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.h45 RegScavenger *RS = NULL) const;
/external/qemu/tcg/ppc/
H A Dtcg-target.c396 #define RS(r) ((r)<<21) macro
408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 tcg_out32 (s, MTSPR | RS (0) | CTR);
502 tcg_out32 (s, MTSPR | RS (arg) | LR);
558 | RS (addr_reg)
573 | RS (addr_reg)
605 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
608 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
672 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_re
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/external/llvm/lib/Target/MSP430/
H A DMSP430RegisterInfo.h50 int SPAdj, RegScavenger *RS = NULL) const;
/external/qemu/tcg/ppc64/
H A Dtcg-target.c393 #define RS(r) ((r)<<21) macro
406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
497 tcg_out32 (s, MTSPR | RS (0) | CTR);
509 tcg_out32 (s, MTSPR | RS (arg) | LR);
577 | RS (addr_reg)
587 | RS (addr_re
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/external/llvm/lib/CodeGen/
H A DPrologEpilogInserter.cpp74 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
84 TFI->processFunctionBeforeCalleeSavedScan(Fn, RS);
131 delete RS;
561 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) &&
563 int SFI = RS->getScavengingFrameIndex();
608 if (RS && (int)i == RS->getScavengingFrameIndex())
630 if (RS && (int)i == RS->getScavengingFrameIndex())
644 if (RS
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/external/guava/guava/src/com/google/common/base/
H A DAscii.java335 * relationship shall be: FS is the most inclusive, then GS, then RS,
355 public static final byte RS = 30; field in class:Ascii
/external/llvm/lib/Target/ARM/
H A DARMFrameLowering.h60 RegScavenger *RS) const;
H A DThumb1RegisterInfo.h65 int SPAdj, RegScavenger *RS = NULL) const;
/external/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.h64 int SPAdj, RegScavenger *RS = NULL) const;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXRegisterInfo.h59 RegScavenger *RS=NULL) const;

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