Searched refs:Reg2 (Results 1 - 13 of 13) sorted by relevance
/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 116 unsigned Reg2, bool isKill2) { 118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 114 addRegReg(const MachineInstrBuilder &MIB, unsigned Reg1, bool isKill1, unsigned Reg2, bool isKill2) argument
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H A D | X86FastISel.cpp | 1475 unsigned Reg2 = getRegForValue(Op2); local 1477 if (Reg1 == 0 || Reg2 == 0) 1493 .addReg(Reg1).addReg(Reg2);
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/external/llvm/lib/CodeGen/ |
H A D | AggressiveAntiDepBreaker.h | 101 // UnionGroups - Union Reg1's and Reg2's groups to form a new 104 unsigned UnionGroups(unsigned Reg1, unsigned Reg2);
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H A D | TargetInstrInfoImpl.cpp | 80 unsigned Reg2 = MI->getOperand(Idx2).getReg(); local 91 Reg0 = Reg2; 93 } else if (HasDef && Reg0 == Reg2 && 111 MI->getOperand(Idx1).setReg(Reg2);
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H A D | AggressiveAntiDepBreaker.cpp | 80 unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2) argument 87 unsigned Group2 = GetGroup(Reg2);
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H A D | StrongPHIElimination.cpp | 438 void StrongPHIElimination::unionRegs(unsigned Reg1, unsigned Reg2) { argument 440 Node *Node2 = RegNodeMap[Reg2]->getLeader();
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/external/llvm/include/llvm/MC/ |
H A D | MCRegisterInfo.h | 76 bool contains(unsigned Reg1, unsigned Reg2) const { 77 return contains(Reg1) && contains(Reg2);
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb2SizeReduction.cpp | 603 unsigned Reg2 = MI->getOperand(2).getReg(); local 606 || !isARMLowRegister(Reg2)) 608 if (Reg0 != Reg2) { 636 unsigned Reg2 = MI->getOperand(2).getReg(); local 637 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
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H A D | ARMFastISel.cpp | 2645 unsigned Reg2 = 0; local 2647 Reg2 = getRegForValue(Src2Value); 2648 if (Reg2 == 0) return false; 2661 MIB.addReg(Reg2);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 160 unsigned Reg2 = MI->getOperand(2).getReg(); local 180 unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg(); 184 .addReg(Reg2, getKillRegState(Reg2IsKill)) 191 MI->getOperand(0).setReg(Reg2); 193 MI->getOperand(1).setReg(Reg2);
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/external/llvm/include/llvm/Target/ |
H A D | TargetRegisterInfo.h | 80 bool contains(unsigned Reg1, unsigned Reg2) const { 81 return MC->contains(Reg1, Reg2);
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/external/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.cpp | 1141 CodeGenRegister *Reg2 = i1->second; local 1143 if (Reg1 == Reg2) 1145 const CodeGenRegister::SubRegMap &SRM2 = Reg2->getSubRegs(); 1152 if (Reg2 == Reg3)
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/external/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 2318 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); local 2319 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 3072 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), local 3074 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
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