1//===-- LegalizeVectorOps.cpp - Implement SelectionDAG::LegalizeVectors ---===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the SelectionDAG::LegalizeVectors method. 11// 12// The vector legalizer looks for vector operations which might need to be 13// scalarized and legalizes them. This is a separate step from Legalize because 14// scalarizing can introduce illegal types. For example, suppose we have an 15// ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition 16// on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the 17// operation, which introduces nodes with the illegal type i64 which must be 18// expanded. Similarly, suppose we have an ISD::SRA of type v16i8 on PowerPC; 19// the operation must be unrolled, which introduces nodes with the illegal 20// type i8 which must be promoted. 21// 22// This does not legalize vector manipulations like ISD::BUILD_VECTOR, 23// or operations that happen to take a vector which are custom-lowered; 24// the legalization for such operations never produces nodes 25// with illegal types, so it's okay to put off legalizing them until 26// SelectionDAG::Legalize runs. 27// 28//===----------------------------------------------------------------------===// 29 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/Target/TargetLowering.h" 32using namespace llvm; 33 34namespace { 35class VectorLegalizer { 36 SelectionDAG& DAG; 37 const TargetLowering &TLI; 38 bool Changed; // Keep track of whether anything changed 39 40 /// LegalizedNodes - For nodes that are of legal width, and that have more 41 /// than one use, this map indicates what regularized operand to use. This 42 /// allows us to avoid legalizing the same thing more than once. 43 DenseMap<SDValue, SDValue> LegalizedNodes; 44 45 // Adds a node to the translation cache 46 void AddLegalizedOperand(SDValue From, SDValue To) { 47 LegalizedNodes.insert(std::make_pair(From, To)); 48 // If someone requests legalization of the new node, return itself. 49 if (From != To) 50 LegalizedNodes.insert(std::make_pair(To, To)); 51 } 52 53 // Legalizes the given node 54 SDValue LegalizeOp(SDValue Op); 55 // Assuming the node is legal, "legalize" the results 56 SDValue TranslateLegalizeResults(SDValue Op, SDValue Result); 57 // Implements unrolling a VSETCC. 58 SDValue UnrollVSETCC(SDValue Op); 59 // Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB 60 // isn't legal. 61 // Implements expansion for UINT_TO_FLOAT; falls back to UnrollVectorOp if 62 // SINT_TO_FLOAT and SHR on vectors isn't legal. 63 SDValue ExpandUINT_TO_FLOAT(SDValue Op); 64 // Implement vselect in terms of XOR, AND, OR when blend is not supported 65 // by the target. 66 SDValue ExpandVSELECT(SDValue Op); 67 SDValue ExpandSELECT(SDValue Op); 68 SDValue ExpandLoad(SDValue Op); 69 SDValue ExpandStore(SDValue Op); 70 SDValue ExpandFNEG(SDValue Op); 71 // Implements vector promotion; this is essentially just bitcasting the 72 // operands to a different type and bitcasting the result back to the 73 // original type. 74 SDValue PromoteVectorOp(SDValue Op); 75 // Implements [SU]INT_TO_FP vector promotion; this is a [zs]ext of the input 76 // operand to the next size up. 77 SDValue PromoteVectorOpINT_TO_FP(SDValue Op); 78 79 public: 80 bool Run(); 81 VectorLegalizer(SelectionDAG& dag) : 82 DAG(dag), TLI(dag.getTargetLoweringInfo()), Changed(false) {} 83}; 84 85bool VectorLegalizer::Run() { 86 // The legalize process is inherently a bottom-up recursive process (users 87 // legalize their uses before themselves). Given infinite stack space, we 88 // could just start legalizing on the root and traverse the whole graph. In 89 // practice however, this causes us to run out of stack space on large basic 90 // blocks. To avoid this problem, compute an ordering of the nodes where each 91 // node is only legalized after all of its operands are legalized. 92 DAG.AssignTopologicalOrder(); 93 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 94 E = prior(DAG.allnodes_end()); I != llvm::next(E); ++I) 95 LegalizeOp(SDValue(I, 0)); 96 97 // Finally, it's possible the root changed. Get the new root. 98 SDValue OldRoot = DAG.getRoot(); 99 assert(LegalizedNodes.count(OldRoot) && "Root didn't get legalized?"); 100 DAG.setRoot(LegalizedNodes[OldRoot]); 101 102 LegalizedNodes.clear(); 103 104 // Remove dead nodes now. 105 DAG.RemoveDeadNodes(); 106 107 return Changed; 108} 109 110SDValue VectorLegalizer::TranslateLegalizeResults(SDValue Op, SDValue Result) { 111 // Generic legalization: just pass the operand through. 112 for (unsigned i = 0, e = Op.getNode()->getNumValues(); i != e; ++i) 113 AddLegalizedOperand(Op.getValue(i), Result.getValue(i)); 114 return Result.getValue(Op.getResNo()); 115} 116 117SDValue VectorLegalizer::LegalizeOp(SDValue Op) { 118 // Note that LegalizeOp may be reentered even from single-use nodes, which 119 // means that we always must cache transformed nodes. 120 DenseMap<SDValue, SDValue>::iterator I = LegalizedNodes.find(Op); 121 if (I != LegalizedNodes.end()) return I->second; 122 123 SDNode* Node = Op.getNode(); 124 125 // Legalize the operands 126 SmallVector<SDValue, 8> Ops; 127 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 128 Ops.push_back(LegalizeOp(Node->getOperand(i))); 129 130 SDValue Result = 131 SDValue(DAG.UpdateNodeOperands(Op.getNode(), Ops.data(), Ops.size()), 0); 132 133 if (Op.getOpcode() == ISD::LOAD) { 134 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 135 ISD::LoadExtType ExtType = LD->getExtensionType(); 136 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { 137 if (TLI.isLoadExtLegal(LD->getExtensionType(), LD->getMemoryVT())) 138 return TranslateLegalizeResults(Op, Result); 139 Changed = true; 140 return LegalizeOp(ExpandLoad(Op)); 141 } 142 } else if (Op.getOpcode() == ISD::STORE) { 143 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); 144 EVT StVT = ST->getMemoryVT(); 145 EVT ValVT = ST->getValue().getValueType(); 146 if (StVT.isVector() && ST->isTruncatingStore()) 147 switch (TLI.getTruncStoreAction(ValVT, StVT)) { 148 default: llvm_unreachable("This action is not supported yet!"); 149 case TargetLowering::Legal: 150 return TranslateLegalizeResults(Op, Result); 151 case TargetLowering::Custom: 152 Changed = true; 153 return LegalizeOp(TLI.LowerOperation(Result, DAG)); 154 case TargetLowering::Expand: 155 Changed = true; 156 return LegalizeOp(ExpandStore(Op)); 157 } 158 } 159 160 bool HasVectorValue = false; 161 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end(); 162 J != E; 163 ++J) 164 HasVectorValue |= J->isVector(); 165 if (!HasVectorValue) 166 return TranslateLegalizeResults(Op, Result); 167 168 EVT QueryType; 169 switch (Op.getOpcode()) { 170 default: 171 return TranslateLegalizeResults(Op, Result); 172 case ISD::ADD: 173 case ISD::SUB: 174 case ISD::MUL: 175 case ISD::SDIV: 176 case ISD::UDIV: 177 case ISD::SREM: 178 case ISD::UREM: 179 case ISD::FADD: 180 case ISD::FSUB: 181 case ISD::FMUL: 182 case ISD::FDIV: 183 case ISD::FREM: 184 case ISD::AND: 185 case ISD::OR: 186 case ISD::XOR: 187 case ISD::SHL: 188 case ISD::SRA: 189 case ISD::SRL: 190 case ISD::ROTL: 191 case ISD::ROTR: 192 case ISD::CTLZ: 193 case ISD::CTTZ: 194 case ISD::CTLZ_ZERO_UNDEF: 195 case ISD::CTTZ_ZERO_UNDEF: 196 case ISD::CTPOP: 197 case ISD::SELECT: 198 case ISD::VSELECT: 199 case ISD::SELECT_CC: 200 case ISD::SETCC: 201 case ISD::ZERO_EXTEND: 202 case ISD::ANY_EXTEND: 203 case ISD::TRUNCATE: 204 case ISD::SIGN_EXTEND: 205 case ISD::FP_TO_SINT: 206 case ISD::FP_TO_UINT: 207 case ISD::FNEG: 208 case ISD::FABS: 209 case ISD::FSQRT: 210 case ISD::FSIN: 211 case ISD::FCOS: 212 case ISD::FPOWI: 213 case ISD::FPOW: 214 case ISD::FLOG: 215 case ISD::FLOG2: 216 case ISD::FLOG10: 217 case ISD::FEXP: 218 case ISD::FEXP2: 219 case ISD::FCEIL: 220 case ISD::FTRUNC: 221 case ISD::FRINT: 222 case ISD::FNEARBYINT: 223 case ISD::FFLOOR: 224 case ISD::FMA: 225 case ISD::SIGN_EXTEND_INREG: 226 QueryType = Node->getValueType(0); 227 break; 228 case ISD::FP_ROUND_INREG: 229 QueryType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 230 break; 231 case ISD::SINT_TO_FP: 232 case ISD::UINT_TO_FP: 233 QueryType = Node->getOperand(0).getValueType(); 234 break; 235 } 236 237 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) { 238 case TargetLowering::Promote: 239 switch (Op.getOpcode()) { 240 default: 241 // "Promote" the operation by bitcasting 242 Result = PromoteVectorOp(Op); 243 Changed = true; 244 break; 245 case ISD::SINT_TO_FP: 246 case ISD::UINT_TO_FP: 247 // "Promote" the operation by extending the operand. 248 Result = PromoteVectorOpINT_TO_FP(Op); 249 Changed = true; 250 break; 251 } 252 break; 253 case TargetLowering::Legal: break; 254 case TargetLowering::Custom: { 255 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); 256 if (Tmp1.getNode()) { 257 Result = Tmp1; 258 break; 259 } 260 // FALL THROUGH 261 } 262 case TargetLowering::Expand: 263 if (Node->getOpcode() == ISD::VSELECT) 264 Result = ExpandVSELECT(Op); 265 else if (Node->getOpcode() == ISD::SELECT) 266 Result = ExpandSELECT(Op); 267 else if (Node->getOpcode() == ISD::UINT_TO_FP) 268 Result = ExpandUINT_TO_FLOAT(Op); 269 else if (Node->getOpcode() == ISD::FNEG) 270 Result = ExpandFNEG(Op); 271 else if (Node->getOpcode() == ISD::SETCC) 272 Result = UnrollVSETCC(Op); 273 else 274 Result = DAG.UnrollVectorOp(Op.getNode()); 275 break; 276 } 277 278 // Make sure that the generated code is itself legal. 279 if (Result != Op) { 280 Result = LegalizeOp(Result); 281 Changed = true; 282 } 283 284 // Note that LegalizeOp may be reentered even from single-use nodes, which 285 // means that we always must cache transformed nodes. 286 AddLegalizedOperand(Op, Result); 287 return Result; 288} 289 290SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { 291 // Vector "promotion" is basically just bitcasting and doing the operation 292 // in a different type. For example, x86 promotes ISD::AND on v2i32 to 293 // v1i64. 294 EVT VT = Op.getValueType(); 295 assert(Op.getNode()->getNumValues() == 1 && 296 "Can't promote a vector with multiple results!"); 297 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); 298 DebugLoc dl = Op.getDebugLoc(); 299 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 300 301 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 302 if (Op.getOperand(j).getValueType().isVector()) 303 Operands[j] = DAG.getNode(ISD::BITCAST, dl, NVT, Op.getOperand(j)); 304 else 305 Operands[j] = Op.getOperand(j); 306 } 307 308 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size()); 309 310 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 311} 312 313SDValue VectorLegalizer::PromoteVectorOpINT_TO_FP(SDValue Op) { 314 // INT_TO_FP operations may require the input operand be promoted even 315 // when the type is otherwise legal. 316 EVT VT = Op.getOperand(0).getValueType(); 317 assert(Op.getNode()->getNumValues() == 1 && 318 "Can't promote a vector with multiple results!"); 319 320 // Normal getTypeToPromoteTo() doesn't work here, as that will promote 321 // by widening the vector w/ the same element width and twice the number 322 // of elements. We want the other way around, the same number of elements, 323 // each twice the width. 324 // 325 // Increase the bitwidth of the element to the next pow-of-two 326 // (which is greater than 8 bits). 327 unsigned NumElts = VT.getVectorNumElements(); 328 EVT EltVT = VT.getVectorElementType(); 329 EltVT = EVT::getIntegerVT(*DAG.getContext(), 2 * EltVT.getSizeInBits()); 330 assert(EltVT.isSimple() && "Promoting to a non-simple vector type!"); 331 332 // Build a new vector type and check if it is legal. 333 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 334 335 DebugLoc dl = Op.getDebugLoc(); 336 SmallVector<SDValue, 4> Operands(Op.getNumOperands()); 337 338 unsigned Opc = Op.getOpcode() == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : 339 ISD::SIGN_EXTEND; 340 for (unsigned j = 0; j != Op.getNumOperands(); ++j) { 341 if (Op.getOperand(j).getValueType().isVector()) 342 Operands[j] = DAG.getNode(Opc, dl, NVT, Op.getOperand(j)); 343 else 344 Operands[j] = Op.getOperand(j); 345 } 346 347 return DAG.getNode(Op.getOpcode(), dl, Op.getValueType(), &Operands[0], 348 Operands.size()); 349} 350 351 352SDValue VectorLegalizer::ExpandLoad(SDValue Op) { 353 DebugLoc dl = Op.getDebugLoc(); 354 LoadSDNode *LD = cast<LoadSDNode>(Op.getNode()); 355 SDValue Chain = LD->getChain(); 356 SDValue BasePTR = LD->getBasePtr(); 357 EVT SrcVT = LD->getMemoryVT(); 358 ISD::LoadExtType ExtType = LD->getExtensionType(); 359 360 SmallVector<SDValue, 8> LoadVals; 361 SmallVector<SDValue, 8> LoadChains; 362 unsigned NumElem = SrcVT.getVectorNumElements(); 363 unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8; 364 365 for (unsigned Idx=0; Idx<NumElem; Idx++) { 366 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl, 367 Op.getNode()->getValueType(0).getScalarType(), 368 Chain, BasePTR, LD->getPointerInfo().getWithOffset(Idx * Stride), 369 SrcVT.getScalarType(), 370 LD->isVolatile(), LD->isNonTemporal(), 371 LD->getAlignment()); 372 373 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 374 DAG.getIntPtrConstant(Stride)); 375 376 LoadVals.push_back(ScalarLoad.getValue(0)); 377 LoadChains.push_back(ScalarLoad.getValue(1)); 378 } 379 380 SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 381 &LoadChains[0], LoadChains.size()); 382 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, 383 Op.getNode()->getValueType(0), &LoadVals[0], LoadVals.size()); 384 385 AddLegalizedOperand(Op.getValue(0), Value); 386 AddLegalizedOperand(Op.getValue(1), NewChain); 387 388 return (Op.getResNo() ? NewChain : Value); 389} 390 391SDValue VectorLegalizer::ExpandStore(SDValue Op) { 392 DebugLoc dl = Op.getDebugLoc(); 393 StoreSDNode *ST = cast<StoreSDNode>(Op.getNode()); 394 SDValue Chain = ST->getChain(); 395 SDValue BasePTR = ST->getBasePtr(); 396 SDValue Value = ST->getValue(); 397 EVT StVT = ST->getMemoryVT(); 398 399 unsigned Alignment = ST->getAlignment(); 400 bool isVolatile = ST->isVolatile(); 401 bool isNonTemporal = ST->isNonTemporal(); 402 403 unsigned NumElem = StVT.getVectorNumElements(); 404 // The type of the data we want to save 405 EVT RegVT = Value.getValueType(); 406 EVT RegSclVT = RegVT.getScalarType(); 407 // The type of data as saved in memory. 408 EVT MemSclVT = StVT.getScalarType(); 409 410 // Cast floats into integers 411 unsigned ScalarSize = MemSclVT.getSizeInBits(); 412 413 // Round odd types to the next pow of two. 414 if (!isPowerOf2_32(ScalarSize)) 415 ScalarSize = NextPowerOf2(ScalarSize); 416 417 // Store Stride in bytes 418 unsigned Stride = ScalarSize/8; 419 // Extract each of the elements from the original vector 420 // and save them into memory individually. 421 SmallVector<SDValue, 8> Stores; 422 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 423 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 424 RegSclVT, Value, DAG.getIntPtrConstant(Idx)); 425 426 // This scalar TruncStore may be illegal, but we legalize it later. 427 SDValue Store = DAG.getTruncStore(Chain, dl, Ex, BasePTR, 428 ST->getPointerInfo().getWithOffset(Idx*Stride), MemSclVT, 429 isVolatile, isNonTemporal, Alignment); 430 431 BasePTR = DAG.getNode(ISD::ADD, dl, BasePTR.getValueType(), BasePTR, 432 DAG.getIntPtrConstant(Stride)); 433 434 Stores.push_back(Store); 435 } 436 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 437 &Stores[0], Stores.size()); 438 AddLegalizedOperand(Op, TF); 439 return TF; 440} 441 442SDValue VectorLegalizer::ExpandSELECT(SDValue Op) { 443 // Lower a select instruction where the condition is a scalar and the 444 // operands are vectors. Lower this select to VSELECT and implement it 445 // using XOR AND OR. The selector bit is broadcasted. 446 EVT VT = Op.getValueType(); 447 DebugLoc DL = Op.getDebugLoc(); 448 449 SDValue Mask = Op.getOperand(0); 450 SDValue Op1 = Op.getOperand(1); 451 SDValue Op2 = Op.getOperand(2); 452 453 assert(VT.isVector() && !Mask.getValueType().isVector() 454 && Op1.getValueType() == Op2.getValueType() && "Invalid type"); 455 456 unsigned NumElem = VT.getVectorNumElements(); 457 458 // If we can't even use the basic vector operations of 459 // AND,OR,XOR, we will have to scalarize the op. 460 // Notice that the operation may be 'promoted' which means that it is 461 // 'bitcasted' to another type which is handled. 462 // Also, we need to be able to construct a splat vector using BUILD_VECTOR. 463 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || 464 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || 465 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || 466 TLI.getOperationAction(ISD::BUILD_VECTOR, VT) == TargetLowering::Expand) 467 return DAG.UnrollVectorOp(Op.getNode()); 468 469 // Generate a mask operand. 470 EVT MaskTy = TLI.getSetCCResultType(VT); 471 assert(MaskTy.isVector() && "Invalid CC type"); 472 assert(MaskTy.getSizeInBits() == Op1.getValueType().getSizeInBits() 473 && "Invalid mask size"); 474 475 // What is the size of each element in the vector mask. 476 EVT BitTy = MaskTy.getScalarType(); 477 478 Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask, 479 DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy), 480 DAG.getConstant(0, BitTy)); 481 482 // Broadcast the mask so that the entire vector is all-one or all zero. 483 SmallVector<SDValue, 8> Ops(NumElem, Mask); 484 Mask = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskTy, &Ops[0], Ops.size()); 485 486 // Bitcast the operands to be the same type as the mask. 487 // This is needed when we select between FP types because 488 // the mask is a vector of integers. 489 Op1 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op1); 490 Op2 = DAG.getNode(ISD::BITCAST, DL, MaskTy, Op2); 491 492 SDValue AllOnes = DAG.getConstant( 493 APInt::getAllOnesValue(BitTy.getSizeInBits()), MaskTy); 494 SDValue NotMask = DAG.getNode(ISD::XOR, DL, MaskTy, Mask, AllOnes); 495 496 Op1 = DAG.getNode(ISD::AND, DL, MaskTy, Op1, Mask); 497 Op2 = DAG.getNode(ISD::AND, DL, MaskTy, Op2, NotMask); 498 SDValue Val = DAG.getNode(ISD::OR, DL, MaskTy, Op1, Op2); 499 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 500} 501 502SDValue VectorLegalizer::ExpandVSELECT(SDValue Op) { 503 // Implement VSELECT in terms of XOR, AND, OR 504 // on platforms which do not support blend natively. 505 EVT VT = Op.getOperand(0).getValueType(); 506 DebugLoc DL = Op.getDebugLoc(); 507 508 SDValue Mask = Op.getOperand(0); 509 SDValue Op1 = Op.getOperand(1); 510 SDValue Op2 = Op.getOperand(2); 511 512 // If we can't even use the basic vector operations of 513 // AND,OR,XOR, we will have to scalarize the op. 514 // Notice that the operation may be 'promoted' which means that it is 515 // 'bitcasted' to another type which is handled. 516 // This operation also isn't safe with AND, OR, XOR when the boolean 517 // type is 0/1 as we need an all ones vector constant to mask with. 518 // FIXME: Sign extend 1 to all ones if thats legal on the target. 519 if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand || 520 TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand || 521 TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand || 522 TLI.getBooleanContents(true) != 523 TargetLowering::ZeroOrNegativeOneBooleanContent) 524 return DAG.UnrollVectorOp(Op.getNode()); 525 526 assert(VT.getSizeInBits() == Op1.getValueType().getSizeInBits() 527 && "Invalid mask size"); 528 // Bitcast the operands to be the same type as the mask. 529 // This is needed when we select between FP types because 530 // the mask is a vector of integers. 531 Op1 = DAG.getNode(ISD::BITCAST, DL, VT, Op1); 532 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2); 533 534 SDValue AllOnes = DAG.getConstant( 535 APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()), VT); 536 SDValue NotMask = DAG.getNode(ISD::XOR, DL, VT, Mask, AllOnes); 537 538 Op1 = DAG.getNode(ISD::AND, DL, VT, Op1, Mask); 539 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask); 540 SDValue Val = DAG.getNode(ISD::OR, DL, VT, Op1, Op2); 541 return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Val); 542} 543 544SDValue VectorLegalizer::ExpandUINT_TO_FLOAT(SDValue Op) { 545 EVT VT = Op.getOperand(0).getValueType(); 546 DebugLoc DL = Op.getDebugLoc(); 547 548 // Make sure that the SINT_TO_FP and SRL instructions are available. 549 if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand || 550 TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand) 551 return DAG.UnrollVectorOp(Op.getNode()); 552 553 EVT SVT = VT.getScalarType(); 554 assert((SVT.getSizeInBits() == 64 || SVT.getSizeInBits() == 32) && 555 "Elements in vector-UINT_TO_FP must be 32 or 64 bits wide"); 556 557 unsigned BW = SVT.getSizeInBits(); 558 SDValue HalfWord = DAG.getConstant(BW/2, VT); 559 560 // Constants to clear the upper part of the word. 561 // Notice that we can also use SHL+SHR, but using a constant is slightly 562 // faster on x86. 563 uint64_t HWMask = (SVT.getSizeInBits()==64)?0x00000000FFFFFFFF:0x0000FFFF; 564 SDValue HalfWordMask = DAG.getConstant(HWMask, VT); 565 566 // Two to the power of half-word-size. 567 SDValue TWOHW = DAG.getConstantFP((1<<(BW/2)), Op.getValueType()); 568 569 // Clear upper part of LO, lower HI 570 SDValue HI = DAG.getNode(ISD::SRL, DL, VT, Op.getOperand(0), HalfWord); 571 SDValue LO = DAG.getNode(ISD::AND, DL, VT, Op.getOperand(0), HalfWordMask); 572 573 // Convert hi and lo to floats 574 // Convert the hi part back to the upper values 575 SDValue fHI = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), HI); 576 fHI = DAG.getNode(ISD::FMUL, DL, Op.getValueType(), fHI, TWOHW); 577 SDValue fLO = DAG.getNode(ISD::SINT_TO_FP, DL, Op.getValueType(), LO); 578 579 // Add the two halves 580 return DAG.getNode(ISD::FADD, DL, Op.getValueType(), fHI, fLO); 581} 582 583 584SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { 585 if (TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) { 586 SDValue Zero = DAG.getConstantFP(-0.0, Op.getValueType()); 587 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 588 Zero, Op.getOperand(0)); 589 } 590 return DAG.UnrollVectorOp(Op.getNode()); 591} 592 593SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { 594 EVT VT = Op.getValueType(); 595 unsigned NumElems = VT.getVectorNumElements(); 596 EVT EltVT = VT.getVectorElementType(); 597 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); 598 EVT TmpEltVT = LHS.getValueType().getVectorElementType(); 599 DebugLoc dl = Op.getDebugLoc(); 600 SmallVector<SDValue, 8> Ops(NumElems); 601 for (unsigned i = 0; i < NumElems; ++i) { 602 SDValue LHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, LHS, 603 DAG.getIntPtrConstant(i)); 604 SDValue RHSElem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, TmpEltVT, RHS, 605 DAG.getIntPtrConstant(i)); 606 Ops[i] = DAG.getNode(ISD::SETCC, dl, TLI.getSetCCResultType(TmpEltVT), 607 LHSElem, RHSElem, CC); 608 Ops[i] = DAG.getNode(ISD::SELECT, dl, EltVT, Ops[i], 609 DAG.getConstant(APInt::getAllOnesValue 610 (EltVT.getSizeInBits()), EltVT), 611 DAG.getConstant(0, EltVT)); 612 } 613 return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems); 614} 615 616} 617 618bool SelectionDAG::LegalizeVectors() { 619 return VectorLegalizer(*this).Run(); 620} 621