1//===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the base ARM implementation of TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "ARMBaseRegisterInfo.h" 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMFrameLowering.h" 18#include "ARMMachineFunctionInfo.h" 19#include "ARMSubtarget.h" 20#include "MCTargetDesc/ARMAddressingModes.h" 21#include "llvm/Constants.h" 22#include "llvm/DerivedTypes.h" 23#include "llvm/Function.h" 24#include "llvm/LLVMContext.h" 25#include "llvm/CodeGen/MachineConstantPool.h" 26#include "llvm/CodeGen/MachineFrameInfo.h" 27#include "llvm/CodeGen/MachineFunction.h" 28#include "llvm/CodeGen/MachineInstrBuilder.h" 29#include "llvm/CodeGen/MachineRegisterInfo.h" 30#include "llvm/CodeGen/RegisterScavenging.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetFrameLowering.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include "llvm/ADT/BitVector.h" 38#include "llvm/ADT/SmallVector.h" 39#include "llvm/Support/CommandLine.h" 40 41#define GET_REGINFO_TARGET_DESC 42#include "ARMGenRegisterInfo.inc" 43 44using namespace llvm; 45 46static cl::opt<bool> 47ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false), 48 cl::desc("Force use of virtual base registers for stack load/store")); 49static cl::opt<bool> 50EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden, 51 cl::desc("Enable pre-regalloc stack frame index allocation")); 52static cl::opt<bool> 53EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true), 54 cl::desc("Enable use of a base pointer for complex stack frames")); 55 56ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, 57 const ARMSubtarget &sti) 58 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti), 59 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), 60 BasePtr(ARM::R6) { 61} 62 63const uint16_t* 64ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 65 bool ghcCall = false; 66 67 if (MF) { 68 const Function *F = MF->getFunction(); 69 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 70 } 71 72 if (ghcCall) { 73 return CSR_GHC_SaveList; 74 } 75 else { 76 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 77 ? CSR_iOS_SaveList : CSR_AAPCS_SaveList; 78 } 79} 80 81const uint32_t* 82ARMBaseRegisterInfo::getCallPreservedMask(CallingConv::ID) const { 83 return (STI.isTargetIOS() && !STI.isAAPCS_ABI()) 84 ? CSR_iOS_RegMask : CSR_AAPCS_RegMask; 85} 86 87BitVector ARMBaseRegisterInfo:: 88getReservedRegs(const MachineFunction &MF) const { 89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 90 91 // FIXME: avoid re-calculating this every time. 92 BitVector Reserved(getNumRegs()); 93 Reserved.set(ARM::SP); 94 Reserved.set(ARM::PC); 95 Reserved.set(ARM::FPSCR); 96 if (TFI->hasFP(MF)) 97 Reserved.set(FramePtr); 98 if (hasBasePointer(MF)) 99 Reserved.set(BasePtr); 100 // Some targets reserve R9. 101 if (STI.isR9Reserved()) 102 Reserved.set(ARM::R9); 103 // Reserve D16-D31 if the subtarget doesn't support them. 104 if (!STI.hasVFP3() || STI.hasD16()) { 105 assert(ARM::D31 == ARM::D16 + 15); 106 for (unsigned i = 0; i != 16; ++i) 107 Reserved.set(ARM::D16 + i); 108 } 109 return Reserved; 110} 111 112bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, 113 unsigned Reg) const { 114 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 115 116 switch (Reg) { 117 default: break; 118 case ARM::SP: 119 case ARM::PC: 120 return true; 121 case ARM::R6: 122 if (hasBasePointer(MF)) 123 return true; 124 break; 125 case ARM::R7: 126 case ARM::R11: 127 if (FramePtr == Reg && TFI->hasFP(MF)) 128 return true; 129 break; 130 case ARM::R9: 131 return STI.isR9Reserved(); 132 } 133 134 return false; 135} 136 137bool 138ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC, 139 SmallVectorImpl<unsigned> &SubIndices, 140 unsigned &NewSubIdx) const { 141 142 unsigned Size = RC->getSize() * 8; 143 if (Size < 6) 144 return 0; 145 146 NewSubIdx = 0; // Whole register. 147 unsigned NumRegs = SubIndices.size(); 148 if (NumRegs == 8) { 149 // 8 D registers -> 1 QQQQ register. 150 return (Size == 512 && 151 SubIndices[0] == ARM::dsub_0 && 152 SubIndices[1] == ARM::dsub_1 && 153 SubIndices[2] == ARM::dsub_2 && 154 SubIndices[3] == ARM::dsub_3 && 155 SubIndices[4] == ARM::dsub_4 && 156 SubIndices[5] == ARM::dsub_5 && 157 SubIndices[6] == ARM::dsub_6 && 158 SubIndices[7] == ARM::dsub_7); 159 } else if (NumRegs == 4) { 160 if (SubIndices[0] == ARM::qsub_0) { 161 // 4 Q registers -> 1 QQQQ register. 162 return (Size == 512 && 163 SubIndices[1] == ARM::qsub_1 && 164 SubIndices[2] == ARM::qsub_2 && 165 SubIndices[3] == ARM::qsub_3); 166 } else if (SubIndices[0] == ARM::dsub_0) { 167 // 4 D registers -> 1 QQ register. 168 if (Size >= 256 && 169 SubIndices[1] == ARM::dsub_1 && 170 SubIndices[2] == ARM::dsub_2 && 171 SubIndices[3] == ARM::dsub_3) { 172 if (Size == 512) 173 NewSubIdx = ARM::qqsub_0; 174 return true; 175 } 176 } else if (SubIndices[0] == ARM::dsub_4) { 177 // 4 D registers -> 1 QQ register (2nd). 178 if (Size == 512 && 179 SubIndices[1] == ARM::dsub_5 && 180 SubIndices[2] == ARM::dsub_6 && 181 SubIndices[3] == ARM::dsub_7) { 182 NewSubIdx = ARM::qqsub_1; 183 return true; 184 } 185 } else if (SubIndices[0] == ARM::ssub_0) { 186 // 4 S registers -> 1 Q register. 187 if (Size >= 128 && 188 SubIndices[1] == ARM::ssub_1 && 189 SubIndices[2] == ARM::ssub_2 && 190 SubIndices[3] == ARM::ssub_3) { 191 if (Size >= 256) 192 NewSubIdx = ARM::qsub_0; 193 return true; 194 } 195 } 196 } else if (NumRegs == 2) { 197 if (SubIndices[0] == ARM::qsub_0) { 198 // 2 Q registers -> 1 QQ register. 199 if (Size >= 256 && SubIndices[1] == ARM::qsub_1) { 200 if (Size == 512) 201 NewSubIdx = ARM::qqsub_0; 202 return true; 203 } 204 } else if (SubIndices[0] == ARM::qsub_2) { 205 // 2 Q registers -> 1 QQ register (2nd). 206 if (Size == 512 && SubIndices[1] == ARM::qsub_3) { 207 NewSubIdx = ARM::qqsub_1; 208 return true; 209 } 210 } else if (SubIndices[0] == ARM::dsub_0) { 211 // 2 D registers -> 1 Q register. 212 if (Size >= 128 && SubIndices[1] == ARM::dsub_1) { 213 if (Size >= 256) 214 NewSubIdx = ARM::qsub_0; 215 return true; 216 } 217 } else if (SubIndices[0] == ARM::dsub_2) { 218 // 2 D registers -> 1 Q register (2nd). 219 if (Size >= 256 && SubIndices[1] == ARM::dsub_3) { 220 NewSubIdx = ARM::qsub_1; 221 return true; 222 } 223 } else if (SubIndices[0] == ARM::dsub_4) { 224 // 2 D registers -> 1 Q register (3rd). 225 if (Size == 512 && SubIndices[1] == ARM::dsub_5) { 226 NewSubIdx = ARM::qsub_2; 227 return true; 228 } 229 } else if (SubIndices[0] == ARM::dsub_6) { 230 // 2 D registers -> 1 Q register (3rd). 231 if (Size == 512 && SubIndices[1] == ARM::dsub_7) { 232 NewSubIdx = ARM::qsub_3; 233 return true; 234 } 235 } else if (SubIndices[0] == ARM::ssub_0) { 236 // 2 S registers -> 1 D register. 237 if (SubIndices[1] == ARM::ssub_1) { 238 if (Size >= 128) 239 NewSubIdx = ARM::dsub_0; 240 return true; 241 } 242 } else if (SubIndices[0] == ARM::ssub_2) { 243 // 2 S registers -> 1 D register (2nd). 244 if (Size >= 128 && SubIndices[1] == ARM::ssub_3) { 245 NewSubIdx = ARM::dsub_1; 246 return true; 247 } 248 } 249 } 250 return false; 251} 252 253const TargetRegisterClass* 254ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) 255 const { 256 const TargetRegisterClass *Super = RC; 257 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 258 do { 259 switch (Super->getID()) { 260 case ARM::GPRRegClassID: 261 case ARM::SPRRegClassID: 262 case ARM::DPRRegClassID: 263 case ARM::QPRRegClassID: 264 case ARM::QQPRRegClassID: 265 case ARM::QQQQPRRegClassID: 266 return Super; 267 } 268 Super = *I++; 269 } while (Super); 270 return RC; 271} 272 273const TargetRegisterClass * 274ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 275 const { 276 return &ARM::GPRRegClass; 277} 278 279const TargetRegisterClass * 280ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 281 if (RC == &ARM::CCRRegClass) 282 return 0; // Can't copy CCR registers. 283 return RC; 284} 285 286unsigned 287ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 288 MachineFunction &MF) const { 289 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 290 291 switch (RC->getID()) { 292 default: 293 return 0; 294 case ARM::tGPRRegClassID: 295 return TFI->hasFP(MF) ? 4 : 5; 296 case ARM::GPRRegClassID: { 297 unsigned FP = TFI->hasFP(MF) ? 1 : 0; 298 return 10 - FP - (STI.isR9Reserved() ? 1 : 0); 299 } 300 case ARM::SPRRegClassID: // Currently not used as 'rep' register class. 301 case ARM::DPRRegClassID: 302 return 32 - 10; 303 } 304} 305 306/// getRawAllocationOrder - Returns the register allocation order for a 307/// specified register class with a target-dependent hint. 308ArrayRef<uint16_t> 309ARMBaseRegisterInfo::getRawAllocationOrder(const TargetRegisterClass *RC, 310 unsigned HintType, unsigned HintReg, 311 const MachineFunction &MF) const { 312 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 313 // Alternative register allocation orders when favoring even / odd registers 314 // of register pairs. 315 316 // No FP, R9 is available. 317 static const uint16_t GPREven1[] = { 318 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10, 319 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, 320 ARM::R9, ARM::R11 321 }; 322 static const uint16_t GPROdd1[] = { 323 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11, 324 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 325 ARM::R8, ARM::R10 326 }; 327 328 // FP is R7, R9 is available. 329 static const uint16_t GPREven2[] = { 330 ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10, 331 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, 332 ARM::R9, ARM::R11 333 }; 334 static const uint16_t GPROdd2[] = { 335 ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11, 336 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, 337 ARM::R8, ARM::R10 338 }; 339 340 // FP is R11, R9 is available. 341 static const uint16_t GPREven3[] = { 342 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, 343 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, 344 ARM::R9 345 }; 346 static const uint16_t GPROdd3[] = { 347 ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9, 348 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7, 349 ARM::R8 350 }; 351 352 // No FP, R9 is not available. 353 static const uint16_t GPREven4[] = { 354 ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10, 355 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8, 356 ARM::R11 357 }; 358 static const uint16_t GPROdd4[] = { 359 ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11, 360 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 361 ARM::R10 362 }; 363 364 // FP is R7, R9 is not available. 365 static const uint16_t GPREven5[] = { 366 ARM::R0, ARM::R2, ARM::R4, ARM::R10, 367 ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8, 368 ARM::R11 369 }; 370 static const uint16_t GPROdd5[] = { 371 ARM::R1, ARM::R3, ARM::R5, ARM::R11, 372 ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8, 373 ARM::R10 374 }; 375 376 // FP is R11, R9 is not available. 377 static const uint16_t GPREven6[] = { 378 ARM::R0, ARM::R2, ARM::R4, ARM::R6, 379 ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8 380 }; 381 static const uint16_t GPROdd6[] = { 382 ARM::R1, ARM::R3, ARM::R5, ARM::R7, 383 ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 384 }; 385 386 // We only support even/odd hints for GPR and rGPR. 387 if (RC != &ARM::GPRRegClass && RC != &ARM::rGPRRegClass) 388 return RC->getRawAllocationOrder(MF); 389 390 if (HintType == ARMRI::RegPairEven) { 391 if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) 392 // It's no longer possible to fulfill this hint. Return the default 393 // allocation order. 394 return RC->getRawAllocationOrder(MF); 395 396 if (!TFI->hasFP(MF)) { 397 if (!STI.isR9Reserved()) 398 return makeArrayRef(GPREven1); 399 else 400 return makeArrayRef(GPREven4); 401 } else if (FramePtr == ARM::R7) { 402 if (!STI.isR9Reserved()) 403 return makeArrayRef(GPREven2); 404 else 405 return makeArrayRef(GPREven5); 406 } else { // FramePtr == ARM::R11 407 if (!STI.isR9Reserved()) 408 return makeArrayRef(GPREven3); 409 else 410 return makeArrayRef(GPREven6); 411 } 412 } else if (HintType == ARMRI::RegPairOdd) { 413 if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0) 414 // It's no longer possible to fulfill this hint. Return the default 415 // allocation order. 416 return RC->getRawAllocationOrder(MF); 417 418 if (!TFI->hasFP(MF)) { 419 if (!STI.isR9Reserved()) 420 return makeArrayRef(GPROdd1); 421 else 422 return makeArrayRef(GPROdd4); 423 } else if (FramePtr == ARM::R7) { 424 if (!STI.isR9Reserved()) 425 return makeArrayRef(GPROdd2); 426 else 427 return makeArrayRef(GPROdd5); 428 } else { // FramePtr == ARM::R11 429 if (!STI.isR9Reserved()) 430 return makeArrayRef(GPROdd3); 431 else 432 return makeArrayRef(GPROdd6); 433 } 434 } 435 return RC->getRawAllocationOrder(MF); 436} 437 438/// ResolveRegAllocHint - Resolves the specified register allocation hint 439/// to a physical register. Returns the physical register if it is successful. 440unsigned 441ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg, 442 const MachineFunction &MF) const { 443 if (Reg == 0 || !isPhysicalRegister(Reg)) 444 return 0; 445 if (Type == 0) 446 return Reg; 447 else if (Type == (unsigned)ARMRI::RegPairOdd) 448 // Odd register. 449 return getRegisterPairOdd(Reg, MF); 450 else if (Type == (unsigned)ARMRI::RegPairEven) 451 // Even register. 452 return getRegisterPairEven(Reg, MF); 453 return 0; 454} 455 456void 457ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg, 458 MachineFunction &MF) const { 459 MachineRegisterInfo *MRI = &MF.getRegInfo(); 460 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 461 if ((Hint.first == (unsigned)ARMRI::RegPairOdd || 462 Hint.first == (unsigned)ARMRI::RegPairEven) && 463 TargetRegisterInfo::isVirtualRegister(Hint.second)) { 464 // If 'Reg' is one of the even / odd register pair and it's now changed 465 // (e.g. coalesced) into a different register. The other register of the 466 // pair allocation hint must be updated to reflect the relationship 467 // change. 468 unsigned OtherReg = Hint.second; 469 Hint = MRI->getRegAllocationHint(OtherReg); 470 if (Hint.second == Reg) 471 // Make sure the pair has not already divorced. 472 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 473 } 474} 475 476bool 477ARMBaseRegisterInfo::avoidWriteAfterWrite(const TargetRegisterClass *RC) const { 478 // CortexA9 has a Write-after-write hazard for NEON registers. 479 if (!STI.isCortexA9()) 480 return false; 481 482 switch (RC->getID()) { 483 case ARM::DPRRegClassID: 484 case ARM::DPR_8RegClassID: 485 case ARM::DPR_VFP2RegClassID: 486 case ARM::QPRRegClassID: 487 case ARM::QPR_8RegClassID: 488 case ARM::QPR_VFP2RegClassID: 489 case ARM::SPRRegClassID: 490 case ARM::SPR_8RegClassID: 491 // Avoid reusing S, D, and Q registers. 492 // Don't increase register pressure for QQ and QQQQ. 493 return true; 494 default: 495 return false; 496 } 497} 498 499bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const { 500 const MachineFrameInfo *MFI = MF.getFrameInfo(); 501 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 502 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 503 504 if (!EnableBasePointer) 505 return false; 506 507 // When outgoing call frames are so large that we adjust the stack pointer 508 // around the call, we can no longer use the stack pointer to reach the 509 // emergency spill slot. 510 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF)) 511 return true; 512 513 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited 514 // negative range for ldr/str (255), and thumb1 is positive offsets only. 515 // It's going to be better to use the SP or Base Pointer instead. When there 516 // are variable sized objects, we can't reference off of the SP, so we 517 // reserve a Base Pointer. 518 if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) { 519 // Conservatively estimate whether the negative offset from the frame 520 // pointer will be sufficient to reach. If a function has a smallish 521 // frame, it's less likely to have lots of spills and callee saved 522 // space, so it's all more likely to be within range of the frame pointer. 523 // If it's wrong, the scavenger will still enable access to work, it just 524 // won't be optimal. 525 if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128) 526 return false; 527 return true; 528 } 529 530 return false; 531} 532 533bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const { 534 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 535 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 536 // We can't realign the stack if: 537 // 1. Dynamic stack realignment is explicitly disabled, 538 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or 539 // 3. There are VLAs in the function and the base pointer is disabled. 540 if (!MF.getTarget().Options.RealignStack) 541 return false; 542 if (AFI->isThumb1OnlyFunction()) 543 return false; 544 // Stack realignment requires a frame pointer. If we already started 545 // register allocation with frame pointer elimination, it is too late now. 546 if (!MRI->canReserveReg(FramePtr)) 547 return false; 548 // We may also need a base pointer if there are dynamic allocas or stack 549 // pointer adjustments around calls. 550 if (MF.getTarget().getFrameLowering()->hasReservedCallFrame(MF)) 551 return true; 552 if (!EnableBasePointer) 553 return false; 554 // A base pointer is required and allowed. Check that it isn't too late to 555 // reserve it. 556 return MRI->canReserveReg(BasePtr); 557} 558 559bool ARMBaseRegisterInfo:: 560needsStackRealignment(const MachineFunction &MF) const { 561 const MachineFrameInfo *MFI = MF.getFrameInfo(); 562 const Function *F = MF.getFunction(); 563 unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); 564 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 565 F->hasFnAttr(Attribute::StackAlignment)); 566 567 return requiresRealignment && canRealignStack(MF); 568} 569 570bool ARMBaseRegisterInfo:: 571cannotEliminateFrame(const MachineFunction &MF) const { 572 const MachineFrameInfo *MFI = MF.getFrameInfo(); 573 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI->adjustsStack()) 574 return true; 575 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() 576 || needsStackRealignment(MF); 577} 578 579unsigned 580ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { 581 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 582 583 if (TFI->hasFP(MF)) 584 return FramePtr; 585 return ARM::SP; 586} 587 588unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const { 589 llvm_unreachable("What is the exception register"); 590} 591 592unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const { 593 llvm_unreachable("What is the exception handler register"); 594} 595 596unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, 597 const MachineFunction &MF) const { 598 switch (Reg) { 599 default: break; 600 // Return 0 if either register of the pair is a special register. 601 // So no R12, etc. 602 case ARM::R1: return ARM::R0; 603 case ARM::R3: return ARM::R2; 604 case ARM::R5: return ARM::R4; 605 case ARM::R7: 606 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) 607 ? 0 : ARM::R6; 608 case ARM::R9: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8; 609 case ARM::R11: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10; 610 611 case ARM::S1: return ARM::S0; 612 case ARM::S3: return ARM::S2; 613 case ARM::S5: return ARM::S4; 614 case ARM::S7: return ARM::S6; 615 case ARM::S9: return ARM::S8; 616 case ARM::S11: return ARM::S10; 617 case ARM::S13: return ARM::S12; 618 case ARM::S15: return ARM::S14; 619 case ARM::S17: return ARM::S16; 620 case ARM::S19: return ARM::S18; 621 case ARM::S21: return ARM::S20; 622 case ARM::S23: return ARM::S22; 623 case ARM::S25: return ARM::S24; 624 case ARM::S27: return ARM::S26; 625 case ARM::S29: return ARM::S28; 626 case ARM::S31: return ARM::S30; 627 628 case ARM::D1: return ARM::D0; 629 case ARM::D3: return ARM::D2; 630 case ARM::D5: return ARM::D4; 631 case ARM::D7: return ARM::D6; 632 case ARM::D9: return ARM::D8; 633 case ARM::D11: return ARM::D10; 634 case ARM::D13: return ARM::D12; 635 case ARM::D15: return ARM::D14; 636 case ARM::D17: return ARM::D16; 637 case ARM::D19: return ARM::D18; 638 case ARM::D21: return ARM::D20; 639 case ARM::D23: return ARM::D22; 640 case ARM::D25: return ARM::D24; 641 case ARM::D27: return ARM::D26; 642 case ARM::D29: return ARM::D28; 643 case ARM::D31: return ARM::D30; 644 } 645 646 return 0; 647} 648 649unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg, 650 const MachineFunction &MF) const { 651 switch (Reg) { 652 default: break; 653 // Return 0 if either register of the pair is a special register. 654 // So no R12, etc. 655 case ARM::R0: return ARM::R1; 656 case ARM::R2: return ARM::R3; 657 case ARM::R4: return ARM::R5; 658 case ARM::R6: 659 return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6)) 660 ? 0 : ARM::R7; 661 case ARM::R8: return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9; 662 case ARM::R10: return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11; 663 664 case ARM::S0: return ARM::S1; 665 case ARM::S2: return ARM::S3; 666 case ARM::S4: return ARM::S5; 667 case ARM::S6: return ARM::S7; 668 case ARM::S8: return ARM::S9; 669 case ARM::S10: return ARM::S11; 670 case ARM::S12: return ARM::S13; 671 case ARM::S14: return ARM::S15; 672 case ARM::S16: return ARM::S17; 673 case ARM::S18: return ARM::S19; 674 case ARM::S20: return ARM::S21; 675 case ARM::S22: return ARM::S23; 676 case ARM::S24: return ARM::S25; 677 case ARM::S26: return ARM::S27; 678 case ARM::S28: return ARM::S29; 679 case ARM::S30: return ARM::S31; 680 681 case ARM::D0: return ARM::D1; 682 case ARM::D2: return ARM::D3; 683 case ARM::D4: return ARM::D5; 684 case ARM::D6: return ARM::D7; 685 case ARM::D8: return ARM::D9; 686 case ARM::D10: return ARM::D11; 687 case ARM::D12: return ARM::D13; 688 case ARM::D14: return ARM::D15; 689 case ARM::D16: return ARM::D17; 690 case ARM::D18: return ARM::D19; 691 case ARM::D20: return ARM::D21; 692 case ARM::D22: return ARM::D23; 693 case ARM::D24: return ARM::D25; 694 case ARM::D26: return ARM::D27; 695 case ARM::D28: return ARM::D29; 696 case ARM::D30: return ARM::D31; 697 } 698 699 return 0; 700} 701 702/// emitLoadConstPool - Emits a load from constpool to materialize the 703/// specified immediate. 704void ARMBaseRegisterInfo:: 705emitLoadConstPool(MachineBasicBlock &MBB, 706 MachineBasicBlock::iterator &MBBI, 707 DebugLoc dl, 708 unsigned DestReg, unsigned SubIdx, int Val, 709 ARMCC::CondCodes Pred, 710 unsigned PredReg, unsigned MIFlags) const { 711 MachineFunction &MF = *MBB.getParent(); 712 MachineConstantPool *ConstantPool = MF.getConstantPool(); 713 const Constant *C = 714 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val); 715 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4); 716 717 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 718 .addReg(DestReg, getDefRegState(true), SubIdx) 719 .addConstantPoolIndex(Idx) 720 .addImm(0).addImm(Pred).addReg(PredReg) 721 .setMIFlags(MIFlags); 722} 723 724bool ARMBaseRegisterInfo:: 725requiresRegisterScavenging(const MachineFunction &MF) const { 726 return true; 727} 728 729bool ARMBaseRegisterInfo:: 730trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 731 return true; 732} 733 734bool ARMBaseRegisterInfo:: 735requiresFrameIndexScavenging(const MachineFunction &MF) const { 736 return true; 737} 738 739bool ARMBaseRegisterInfo:: 740requiresVirtualBaseRegisters(const MachineFunction &MF) const { 741 return EnableLocalStackAlloc; 742} 743 744static void 745emitSPUpdate(bool isARM, 746 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 747 DebugLoc dl, const ARMBaseInstrInfo &TII, 748 int NumBytes, 749 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { 750 if (isARM) 751 emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 752 Pred, PredReg, TII); 753 else 754 emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, 755 Pred, PredReg, TII); 756} 757 758 759void ARMBaseRegisterInfo:: 760eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 761 MachineBasicBlock::iterator I) const { 762 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 763 if (!TFI->hasReservedCallFrame(MF)) { 764 // If we have alloca, convert as follows: 765 // ADJCALLSTACKDOWN -> sub, sp, sp, amount 766 // ADJCALLSTACKUP -> add, sp, sp, amount 767 MachineInstr *Old = I; 768 DebugLoc dl = Old->getDebugLoc(); 769 unsigned Amount = Old->getOperand(0).getImm(); 770 if (Amount != 0) { 771 // We need to keep the stack aligned properly. To do this, we round the 772 // amount of space needed for the outgoing arguments up to the next 773 // alignment boundary. 774 unsigned Align = TFI->getStackAlignment(); 775 Amount = (Amount+Align-1)/Align*Align; 776 777 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 778 assert(!AFI->isThumb1OnlyFunction() && 779 "This eliminateCallFramePseudoInstr does not support Thumb1!"); 780 bool isARM = !AFI->isThumbFunction(); 781 782 // Replace the pseudo instruction with a new instruction... 783 unsigned Opc = Old->getOpcode(); 784 int PIdx = Old->findFirstPredOperandIdx(); 785 ARMCC::CondCodes Pred = (PIdx == -1) 786 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm(); 787 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) { 788 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN. 789 unsigned PredReg = Old->getOperand(2).getReg(); 790 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); 791 } else { 792 // Note: PredReg is operand 3 for ADJCALLSTACKUP. 793 unsigned PredReg = Old->getOperand(3).getReg(); 794 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP); 795 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); 796 } 797 } 798 } 799 MBB.erase(I); 800} 801 802int64_t ARMBaseRegisterInfo:: 803getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { 804 const MCInstrDesc &Desc = MI->getDesc(); 805 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 806 int64_t InstrOffs = 0; 807 int Scale = 1; 808 unsigned ImmIdx = 0; 809 switch (AddrMode) { 810 case ARMII::AddrModeT2_i8: 811 case ARMII::AddrModeT2_i12: 812 case ARMII::AddrMode_i12: 813 InstrOffs = MI->getOperand(Idx+1).getImm(); 814 Scale = 1; 815 break; 816 case ARMII::AddrMode5: { 817 // VFP address mode. 818 const MachineOperand &OffOp = MI->getOperand(Idx+1); 819 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 820 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 821 InstrOffs = -InstrOffs; 822 Scale = 4; 823 break; 824 } 825 case ARMII::AddrMode2: { 826 ImmIdx = Idx+2; 827 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 828 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 829 InstrOffs = -InstrOffs; 830 break; 831 } 832 case ARMII::AddrMode3: { 833 ImmIdx = Idx+2; 834 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 835 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 836 InstrOffs = -InstrOffs; 837 break; 838 } 839 case ARMII::AddrModeT1_s: { 840 ImmIdx = Idx+1; 841 InstrOffs = MI->getOperand(ImmIdx).getImm(); 842 Scale = 4; 843 break; 844 } 845 default: 846 llvm_unreachable("Unsupported addressing mode!"); 847 } 848 849 return InstrOffs * Scale; 850} 851 852/// needsFrameBaseReg - Returns true if the instruction's frame index 853/// reference would be better served by a base register other than FP 854/// or SP. Used by LocalStackFrameAllocation to determine which frame index 855/// references it should create new base registers for. 856bool ARMBaseRegisterInfo:: 857needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const { 858 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { 859 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 860 } 861 862 // It's the load/store FI references that cause issues, as it can be difficult 863 // to materialize the offset if it won't fit in the literal field. Estimate 864 // based on the size of the local frame and some conservative assumptions 865 // about the rest of the stack frame (note, this is pre-regalloc, so 866 // we don't know everything for certain yet) whether this offset is likely 867 // to be out of range of the immediate. Return true if so. 868 869 // We only generate virtual base registers for loads and stores, so 870 // return false for everything else. 871 unsigned Opc = MI->getOpcode(); 872 switch (Opc) { 873 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12: 874 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12: 875 case ARM::t2LDRi12: case ARM::t2LDRi8: 876 case ARM::t2STRi12: case ARM::t2STRi8: 877 case ARM::VLDRS: case ARM::VLDRD: 878 case ARM::VSTRS: case ARM::VSTRD: 879 case ARM::tSTRspi: case ARM::tLDRspi: 880 if (ForceAllBaseRegAlloc) 881 return true; 882 break; 883 default: 884 return false; 885 } 886 887 // Without a virtual base register, if the function has variable sized 888 // objects, all fixed-size local references will be via the frame pointer, 889 // Approximate the offset and see if it's legal for the instruction. 890 // Note that the incoming offset is based on the SP value at function entry, 891 // so it'll be negative. 892 MachineFunction &MF = *MI->getParent()->getParent(); 893 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 894 MachineFrameInfo *MFI = MF.getFrameInfo(); 895 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 896 897 // Estimate an offset from the frame pointer. 898 // Conservatively assume all callee-saved registers get pushed. R4-R6 899 // will be earlier than the FP, so we ignore those. 900 // R7, LR 901 int64_t FPOffset = Offset - 8; 902 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15 903 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction()) 904 FPOffset -= 80; 905 // Estimate an offset from the stack pointer. 906 // The incoming offset is relating to the SP at the start of the function, 907 // but when we access the local it'll be relative to the SP after local 908 // allocation, so adjust our SP-relative offset by that allocation size. 909 Offset = -Offset; 910 Offset += MFI->getLocalFrameSize(); 911 // Assume that we'll have at least some spill slots allocated. 912 // FIXME: This is a total SWAG number. We should run some statistics 913 // and pick a real one. 914 Offset += 128; // 128 bytes of spill slots 915 916 // If there is a frame pointer, try using it. 917 // The FP is only available if there is no dynamic realignment. We 918 // don't know for sure yet whether we'll need that, so we guess based 919 // on whether there are any local variables that would trigger it. 920 unsigned StackAlign = TFI->getStackAlignment(); 921 if (TFI->hasFP(MF) && 922 !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { 923 if (isFrameOffsetLegal(MI, FPOffset)) 924 return false; 925 } 926 // If we can reference via the stack pointer, try that. 927 // FIXME: This (and the code that resolves the references) can be improved 928 // to only disallow SP relative references in the live range of 929 // the VLA(s). In practice, it's unclear how much difference that 930 // would make, but it may be worth doing. 931 if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset)) 932 return false; 933 934 // The offset likely isn't legal, we want to allocate a virtual base register. 935 return true; 936} 937 938/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to 939/// be a pointer to FrameIdx at the beginning of the basic block. 940void ARMBaseRegisterInfo:: 941materializeFrameBaseRegister(MachineBasicBlock *MBB, 942 unsigned BaseReg, int FrameIdx, 943 int64_t Offset) const { 944 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>(); 945 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : 946 (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri); 947 948 MachineBasicBlock::iterator Ins = MBB->begin(); 949 DebugLoc DL; // Defaults to "unknown" 950 if (Ins != MBB->end()) 951 DL = Ins->getDebugLoc(); 952 953 const MCInstrDesc &MCID = TII.get(ADDriOpc); 954 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 955 const MachineFunction &MF = *MBB->getParent(); 956 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF)); 957 958 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg) 959 .addFrameIndex(FrameIdx).addImm(Offset)); 960 961 if (!AFI->isThumb1OnlyFunction()) 962 AddDefaultCC(MIB); 963} 964 965void 966ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I, 967 unsigned BaseReg, int64_t Offset) const { 968 MachineInstr &MI = *I; 969 MachineBasicBlock &MBB = *MI.getParent(); 970 MachineFunction &MF = *MBB.getParent(); 971 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 972 int Off = Offset; // ARM doesn't need the general 64-bit offsets 973 unsigned i = 0; 974 975 assert(!AFI->isThumb1OnlyFunction() && 976 "This resolveFrameIndex does not support Thumb1!"); 977 978 while (!MI.getOperand(i).isFI()) { 979 ++i; 980 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 981 } 982 bool Done = false; 983 if (!AFI->isThumbFunction()) 984 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII); 985 else { 986 assert(AFI->isThumb2Function()); 987 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII); 988 } 989 assert (Done && "Unable to resolve frame index!"); 990 (void)Done; 991} 992 993bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, 994 int64_t Offset) const { 995 const MCInstrDesc &Desc = MI->getDesc(); 996 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); 997 unsigned i = 0; 998 999 while (!MI->getOperand(i).isFI()) { 1000 ++i; 1001 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!"); 1002 } 1003 1004 // AddrMode4 and AddrMode6 cannot handle any offset. 1005 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6) 1006 return Offset == 0; 1007 1008 unsigned NumBits = 0; 1009 unsigned Scale = 1; 1010 bool isSigned = true; 1011 switch (AddrMode) { 1012 case ARMII::AddrModeT2_i8: 1013 case ARMII::AddrModeT2_i12: 1014 // i8 supports only negative, and i12 supports only positive, so 1015 // based on Offset sign, consider the appropriate instruction 1016 Scale = 1; 1017 if (Offset < 0) { 1018 NumBits = 8; 1019 Offset = -Offset; 1020 } else { 1021 NumBits = 12; 1022 } 1023 break; 1024 case ARMII::AddrMode5: 1025 // VFP address mode. 1026 NumBits = 8; 1027 Scale = 4; 1028 break; 1029 case ARMII::AddrMode_i12: 1030 case ARMII::AddrMode2: 1031 NumBits = 12; 1032 break; 1033 case ARMII::AddrMode3: 1034 NumBits = 8; 1035 break; 1036 case ARMII::AddrModeT1_s: 1037 NumBits = 5; 1038 Scale = 4; 1039 isSigned = false; 1040 break; 1041 default: 1042 llvm_unreachable("Unsupported addressing mode!"); 1043 } 1044 1045 Offset += getFrameIndexInstrOffset(MI, i); 1046 // Make sure the offset is encodable for instructions that scale the 1047 // immediate. 1048 if ((Offset & (Scale-1)) != 0) 1049 return false; 1050 1051 if (isSigned && Offset < 0) 1052 Offset = -Offset; 1053 1054 unsigned Mask = (1 << NumBits) - 1; 1055 if ((unsigned)Offset <= Mask * Scale) 1056 return true; 1057 1058 return false; 1059} 1060 1061void 1062ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 1063 int SPAdj, RegScavenger *RS) const { 1064 unsigned i = 0; 1065 MachineInstr &MI = *II; 1066 MachineBasicBlock &MBB = *MI.getParent(); 1067 MachineFunction &MF = *MBB.getParent(); 1068 const ARMFrameLowering *TFI = 1069 static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering()); 1070 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1071 assert(!AFI->isThumb1OnlyFunction() && 1072 "This eliminateFrameIndex does not support Thumb1!"); 1073 1074 while (!MI.getOperand(i).isFI()) { 1075 ++i; 1076 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 1077 } 1078 1079 int FrameIndex = MI.getOperand(i).getIndex(); 1080 unsigned FrameReg; 1081 1082 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj); 1083 1084 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the 1085 // call frame setup/destroy instructions have already been eliminated. That 1086 // means the stack pointer cannot be used to access the emergency spill slot 1087 // when !hasReservedCallFrame(). 1088#ifndef NDEBUG 1089 if (RS && FrameReg == ARM::SP && FrameIndex == RS->getScavengingFrameIndex()){ 1090 assert(TFI->hasReservedCallFrame(MF) && 1091 "Cannot use SP to access the emergency spill slot in " 1092 "functions without a reserved call frame"); 1093 assert(!MF.getFrameInfo()->hasVarSizedObjects() && 1094 "Cannot use SP to access the emergency spill slot in " 1095 "functions with variable sized frame objects"); 1096 } 1097#endif // NDEBUG 1098 1099 // Special handling of dbg_value instructions. 1100 if (MI.isDebugValue()) { 1101 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/); 1102 MI.getOperand(i+1).ChangeToImmediate(Offset); 1103 return; 1104 } 1105 1106 // Modify MI as necessary to handle as much of 'Offset' as possible 1107 bool Done = false; 1108 if (!AFI->isThumbFunction()) 1109 Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII); 1110 else { 1111 assert(AFI->isThumb2Function()); 1112 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII); 1113 } 1114 if (Done) 1115 return; 1116 1117 // If we get here, the immediate doesn't fit into the instruction. We folded 1118 // as much as possible above, handle the rest, providing a register that is 1119 // SP+LargeImm. 1120 assert((Offset || 1121 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || 1122 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) && 1123 "This code isn't needed if offset already handled!"); 1124 1125 unsigned ScratchReg = 0; 1126 int PIdx = MI.findFirstPredOperandIdx(); 1127 ARMCC::CondCodes Pred = (PIdx == -1) 1128 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm(); 1129 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 1130 if (Offset == 0) 1131 // Must be addrmode4/6. 1132 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false); 1133 else { 1134 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass); 1135 if (!AFI->isThumbFunction()) 1136 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1137 Offset, Pred, PredReg, TII); 1138 else { 1139 assert(AFI->isThumb2Function()); 1140 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, 1141 Offset, Pred, PredReg, TII); 1142 } 1143 // Update the original instruction to use the scratch register. 1144 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); 1145 } 1146} 1147