History log of /external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
e94ac8871a1ac79bece57335d2abece0feed9c02 03-Aug-2012 Eric Christopher <echristo@apple.com> Add support for the ARM GHC calling convention, this patch was in 3.0,
but somehow managed to be dropped later.

Patch by Karel Gardas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
397fc4874efe9c17e737d4c5c50bd19dc3bf27f5 08-May-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().

The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
afb3b5ebe61b480527de86311d2a0770fc857d38 27-Apr-2012 Evan Cheng <evan.cheng@apple.com> Implement a bastardized ABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6a8c7bf8e72338e55f0f9583e1828f62da165d4a 23-Apr-2012 Preston Gurd <preston.gurd@intel.com> This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.

This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.

This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.

The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().

It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.

It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.

Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.

Patch by Andy Zhang!

Thanks to Jakob and Anton for their reviews.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
420761a0f193e87d08ee1c51b26bba23ab4bac7f 20-Apr-2012 Craig Topper <craig.topper@gmail.com> Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
acf2077ca497980a066e8e7bb81ceec0de82d5da 26-Mar-2012 Craig Topper <craig.topper@gmail.com> Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
98a27acc6b1d4bc4bda6eb122851b3f9b39efeb8 20-Mar-2012 Matt Beaumont-Gay <matthewbg@google.com> remove unused variable

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
aaa1e2f820e61a2f4b878d97599b3ca093bc96ed 20-Mar-2012 Bob Wilson <bob.wilson@apple.com> Require a base pointer for stack realignment when SP may vary dynamically.

ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls. Use hasReservedCallFrame() to
check for both. The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.

<rdar://problem/11075906>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
055a8127c9ffee287807fe7cc1b115d0f40162b0 20-Mar-2012 Bob Wilson <bob.wilson@apple.com> Remove some redundant checks.

ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c1f6f42049696e7357fb4837e1b25dabbaed3fe6 17-Mar-2012 Craig Topper <craig.topper@gmail.com> Reorder includes to match coding standards. Fix an issue or two exposed by that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4f92b5e6163b16d63eb63269c2aec670b55ea19a 06-Mar-2012 Lang Hames <lhames@gmail.com> Split fpscr into two registers: FPSCR and FPSCR_NZCV.

The fpscr register contains both flags (set by FP operations/comparisons) and
control bits. The control bits (FPSCR) should be reserved, since they're always
available and needn't be defined before use. The flag bits (FPSCR_NZCV) should
like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152076 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b6632ba380cf624e60fe16b03d6e21b05dd07724 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
015f228861ef9b337366f92f637d4e8d624bb006 04-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store registers in callee saved register tables to reduce size of static data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
0f9d07fb2526c0acdf7ad9fa6e9c1a97a746c0e9 28-Feb-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Enable ARM base pointer when calling functions with large arguments.

When an outgoing call takes more than 2k of arguments on the stack, we
don't allocate that call frame in the prolog, but adjust the stack
pointer immediately before the call instead.

This causes problems with the emergency spill slot because PEI can't
track stack pointer adjustments on the second pass, and if the outgoing
arguments are too big, SP can't be used to reach the emergency spill
slot at all.

Work around these problems by ensuring there is a base or frame pointer
that can be used to access the emergency spill slot.

<rdar://problem/10917166>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
90f20044ade3712c8b0c3f4ebe47d57ad15ae6ce 22-Feb-2012 Chad Rosier <mcrosier@apple.com> Remove extra semi-colons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c2e08db4e5a8e1b3c253fb07c6eb736dfb66fe59 17-Feb-2012 Lang Hames <lhames@gmail.com> Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE bail on reserved registers. This *should* be safe as of r150786.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1834df8384354217c59e1c5dd8bc091c11b8ca43 16-Feb-2012 Lang Hames <lhames@gmail.com> Oop - r150653 + r150654 broke one of my test cases. Backing out for now...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
afae28b1c67171a567c6f0274a7dede83ac5d8f1 16-Feb-2012 Lang Hames <lhames@gmail.com> FPSCR shouldn't be reserved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 20-Jan-2012 David Blaikie <dblaikie@gmail.com> More dead code removal (using -Wunreachable-code)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3ee7d15284f188672e9e429e9e5cf7b870698677 18-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Implement ARMBaseRegisterInfo::getCallPreservedMask().

Move ARM callee-saved lists into ARMCallingConv.td.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148357 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7255a4e1332ccb69918ebe041dff05f9e4e5815d 05-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Reapply r146997, "Heed spill slot alignment on ARM."

Now that canRealignStack() understands frozen reserved registers, it is
safe to use it for aligned spill instructions.

It will only return true if the registers reserved at the beginning of
register allocation allow for dynamic stack realignment.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
54f3b7a9109d1916cf25ffdb2ed5045f03121b5a 05-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Avoid reserving an ARM base pointer during register allocation.

Once register allocation has started the reserved registers are frozen.

Fix the ARM canRealignStack() hook to respect the frozen register state.
Now the hook returns false if register allocation was started with frame
pointer elimination enabled.

It also returns false if register allocation started without a reserved
base pointer, and stack realignment would require a base pointer. This
bug was breaking oggenc on armv6.

No test case, an upcoming patch will use this functionality to realign
the stack for spill slots when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6d5b7cc235e284130350045a320426afceb82874 03-Jan-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Revert r146997, "Heed spill slot alignment on ARM."

This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
52346e964ff1108729c2b8990b859c10f09a1822 20-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Heed spill slot alignment on ARM.

Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
afff941211526a31f931aa9fcac84ae42ff60ef0 20-Dec-2011 Evan Cheng <evan.cheng@apple.com> ARM target code clean up. Check for iOS, not Darwin where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
570f9a972e02830d1ca223743dd6b4cc4fdf9549 19-Dec-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Emit a getMatchingSuperRegClass() implementation for every target.

Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 02-Dec-2011 Nick Lewycky <nicholas@mxc.ca> Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6690bca623d1f6405b95db5b1760f7ba8436e3fb 20-Oct-2011 Chad Rosier <mcrosier@apple.com> Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
fe04757f5e06ab15208ac0a2ab8d7e83c62b9f0d 18-Oct-2011 Chad Rosier <mcrosier@apple.com> Add support for dynamic stack realignment when in thumb1 mode.
rdar://10288916


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e575499d830008784b11499dae290ad0480c8f9d 11-Oct-2011 Bill Wendling <isanbard@gmail.com> Revert r141529. This is causing failures in the test-suite, like bigstack and ReedSolomon. Boo...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8129d213960bac2c9d01053922866fc0f552462e 10-Oct-2011 Bill Wendling <isanbard@gmail.com> When getting the number of bits necessary for addressing mode
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141529 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
2bfaf521aed6d486b2d80dbf12b84b456100cb47 01-Oct-2011 Chad Rosier <mcrosier@apple.com> Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."
to appease nightly testers. Not quite there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140953 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
52490411259ccc34b8c59f3532e78442a46fffd7 01-Oct-2011 Chad Rosier <mcrosier@apple.com> Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact
useful if an optimization assumes the stack has been realigned. Credit to
Eli for his assistance.
rdar://10043857

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140924 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c8e2bb68bbc4a71cc10084c8f89565b9f05e12ef 01-Oct-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Store sub-class lists as a bit vector.

This uses less memory and it reduces the complexity of sub-class
operations:

- hasSubClassEq() and friends become O(1) instead of O(N).

- getCommonSubClass() becomes O(N) instead of O(N^2).

In the future, TableGen will infer register classes. This makes it
cheap to add them.

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/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8f310d978681b08e2e134a1d7b0433e43aa909f2 13-Sep-2011 Jim Grosbach <grosbach@apple.com> Tidy up a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
342e3161d9dd4fa485b47788aa0266f9c91c3832 30-Aug-2011 Evan Cheng <evan.cheng@apple.com> Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.

When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube

If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.

subc
|
libcall #2
|
libcall #1
|
sube

However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.

The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.

rdar://10019576


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5b81584f7403ffdb9cc6babaaeb0411c080e0f81 24-Aug-2011 Jim Grosbach <grosbach@apple.com> Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.

Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1f6a329f79b3568d379142f921f59c4143ddaa14 12-Aug-2011 Duncan Sands <baldrick@free.fr> Silence a bunch (but not all) "variable written but not read" warnings
when building with assertions disabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137460 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ee04a6d3a40c3017124e3fd89a0db473a2824498 21-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
2d28617de2b0b731c08d1af9e830f31e14ac75b4 19-Jul-2011 Evan Cheng <evan.cheng@apple.com> Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for
better location welcome).


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/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
0e6a052331f674dd70e28af41f654a7874405eab 18-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
39b5abf507b43da6b92f68b86406e0015ead18e9 18-Jul-2011 Frits van Bommel <fvbommel@gmail.com> Migrate LLVM and Clang to use the new makeArrayRef(...) functions where previously explicit non-default constructors were used.
Mostly mechanical with some manual reformatting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c60f9b752381baa6c4b80c0739034660f1748c84 14-Jul-2011 Evan Cheng <evan.cheng@apple.com> Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f6fd90910a552ad9883f031350ae517e26dfdb44 30-Jun-2011 Jim Grosbach <grosbach@apple.com> Remove redundant Thumb2 ADD/SUB SP instruction definitions.

Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d5b03f252c0db6b49a242abab63d7c5a260fceae 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6844f7bcdec8c2691c8d1067d90e4a02cf658c27 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> Hide more details in tablegen generated MCRegisterInfo ctor function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
15993f83a419950f06d2879d6701530ae6449317 27-Jun-2011 Evan Cheng <evan.cheng@apple.com> More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
73f50d9bc3bd46cc0abeba9bb0d46977ba1aea42 27-Jun-2011 Evan Cheng <evan.cheng@apple.com> Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc
into XXXGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d 24-Jun-2011 Evan Cheng <evan.cheng@apple.com> Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3b6434e360315849a65b1ac85e16d160131a77a4 18-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Reserve D16-D13 on subtargets that don't support them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e1fd84af7affc08cda70a4c8261f52ac83195bc4 17-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Explicitly invoke ArrayRef constructor to keep gcc happy.

Patch by Richard Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
dd5a8471526ceadf9bceb1a1221299b3db49c33a 17-Jun-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Rename TRI::getAllocationOrder() to getRawAllocationOrder().

Also switch the return type to ArrayRef<unsigned> which works out nicely
for ARM's implementation of this function because of the clever ArrayRef
constructors.

The name change indicates that the returned allocation order may contain
reserved registers as has been the case for a while.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133216 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6e032942cf58d1c41f88609a1cec74eb74940ecd 30-May-2011 Rafael Espindola <rafael.espindola@gmail.com> Use the dwarf->llvm mapping to print register names in the cfi
directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
462b6dc6bfd95b82eb8a0d2bd8f15a76e7b15957 19-May-2011 Cameron Zwarich <zwarich@apple.com> Reuse the TargetInstrDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
21803721d538255e4d223c29b6c8d3c9e93d4d86 19-May-2011 Cameron Zwarich <zwarich@apple.com> Correctly constrain a register class when computing frame offsets, as the Thumb2
add instruction takes an rGPR. This fixes the last of PR8825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c9e5015dece0a1a73bec358e11bc87594831279d 26-Apr-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.

The hook will be used by the register allocator when recomputing register
classes after removing constraints.

Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee 19-Apr-2011 Bob Wilson <bob.wilson@apple.com> Avoid write-after-write issue hazards for Cortex-A9.

Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.

This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7a2bdde0a0eebcd2125055e0eacaca040f0b766c 15-Apr-2011 Chris Lattner <sabre@nondot.org> Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
eb5067e0d9ca182f21db24949b63616ce4bb1eaf 25-Mar-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Ignore special ARM allocation hints for unexpected register classes.

Add an assertion to linear scan to prevent it from allocating registers outside
the register class.

<rdar://problem/9183021>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
be2119e8e2bc7006cfd638a24367acbfda625d16 07-Mar-2011 Cameron Zwarich <zwarich@apple.com> Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3daccd82d3151fa3629de430b55698a81084fc9e 05-Mar-2011 Anton Korobeynikov <asl@math.spbu.ru> Implement frame unwinding information emission for Thumb1. Not finished yet because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
16c29b5f285f375be53dabaa73e3e91107485fe4 10-Jan-2011 Anton Korobeynikov <asl@math.spbu.ru> Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c9df025e33ac435adb3b3318d237c36ca7cec659 10-Jan-2011 Jakob Stoklund Olesen <stoklund@2pi.dk> Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.

These functions not longer assert when passed 0, but simply return false instead.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
976ef86689ed065361a748f81c44ca3510af2202 18-Dec-2010 Bill Wendling <isanbard@gmail.com> During local stack slot allocation, the materializeFrameBaseRegister function
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122104 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
cde31293d45f14ddff482d385429d256bd4e0820 09-Dec-2010 Jim Grosbach <grosbach@apple.com> When using multiple instructions to reference a frame index, make sure to
update the opcode when necessary as well as the source register.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
94c5ae08750f314bc3cf1bf882b686244a3927d9 28-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move more PEI-related hooks to TFI

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ab5c703fdb0b07c6d89271519fd1cca7105b3eae 22-Nov-2010 Evan Cheng <evan.cheng@apple.com> Fix epilogue codegen to avoid leaving the stack pointer in an invalid
state. Previously Thumb2 would restore sp from fp like this:
mov sp, r7
sub, sp, #4
If an interrupt is taken after the 'mov' but before the 'sub', callee-saved
registers might be clobbered by the interrupt handler. Instead, try
restoring directly from sp:
add sp, #4
Or, if necessary (with VLA, etc.) use a scratch register to compute sp and
then restore it:
sub.w r4, r7, #8
mov sp, r7
rdar://8465407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119977 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
82f58740c76b42af8370247b23677a0318f6dde8 20-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move some more hooks to TargetFrameInfo

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d0c38176690e9602a93a20a43f1bd084564a8116 18-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> Move hasFP() and few related hooks to TargetFrameInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1b4886dd00578038c0ca70b3bab97382b89def26 18-Nov-2010 Evan Cheng <evan.cheng@apple.com> Code clean up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
33464912237efaa0ed7060829e66b59055bdd48b 15-Nov-2010 Anton Korobeynikov <asl@math.spbu.ru> First step of huge frame-related refactoring: move emit{Prologue,Epilogue} out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6c50119ba33bf22885d2229726c809539a85c247 11-Nov-2010 Eric Christopher <echristo@apple.com> Revert this temporarily.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118827 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
391f228e7e00f62b79ad483b801f5f58f046b7ea 11-Nov-2010 Eric Christopher <echristo@apple.com> Change the prologue and epilogue to use push/pop for the low ARM registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ab3d00e5350fd4c097e2a5b077da7584692029a7 02-Nov-2010 Jim Grosbach <grosbach@apple.com> Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke
assumptions about stack layout. Specifically, LR must be saved next to FP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7e3383c007f53b3a00675af225e428cb66ddf404 28-Oct-2010 Jim Grosbach <grosbach@apple.com> Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c1d30212e911d1e55ff6b25bffefb503708883c3 27-Oct-2010 Jim Grosbach <grosbach@apple.com> Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on
rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3e5561247202bae994dd259a2d8dc4eff8f799f3 27-Oct-2010 Jim Grosbach <grosbach@apple.com> First part of refactoring ARM addrmode2 (load/store) instructions to be more
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c3baf62800b149bbd966e5dcd11bce498f428b72 26-Oct-2010 Jim Grosbach <grosbach@apple.com> Nuke extraneous comment. It's applicable elsewhere, but not in this func.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f6d7df6f21abcf15cfa10a6ac7fbb2f7c959093d 20-Oct-2010 Jim Grosbach <grosbach@apple.com> Nuke a commented out bit that got missed a while back.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5c57639c283479a7b1c66e27a745d31b310291c4 18-Oct-2010 Jim Grosbach <grosbach@apple.com> For Thumb2, try to use frame pointer references for stack slots even when a
base register is available. rdar://8525298

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
0f0127f4a686ed55e5b8344d576999259f8c2297 18-Oct-2010 Jim Grosbach <grosbach@apple.com> ARM addrmode4 instructions (ldm, stm and friends) can't encode an immediate
offset for stack references. Make sure we take that into account when
deciding whether to reserver an emergency spill slot for the register
scavenger. rdar://8559625

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e038a206df7df6f799be8e3a308101b77a3414ce 18-Oct-2010 Jim Grosbach <grosbach@apple.com> Grammar tweak.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1dc335a79f5e899aacc6710dfe08ef20abb6a6c0 20-Sep-2010 Jim Grosbach <grosbach@apple.com> Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
push {r4, r5, r6, r7, lr}
add r7, sp, #12
stmdb sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
push {r4, r5, r6, r7, r8, r10, r11, lr}
add r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a4c3c8f28d9465dc7c42eb43c2377530f1821574 15-Sep-2010 Jim Grosbach <grosbach@apple.com> move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f1c3eb37ae96572e1df34bf980b9ecd149b5ee33 15-Sep-2010 Jim Grosbach <grosbach@apple.com> simplify getRegisterNumbering(). Remove the unused isSPVFP argument and
merge the common cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d0bd76b0fb27830f18e15e3d73f2e383ff1c59f1 08-Sep-2010 Jim Grosbach <grosbach@apple.com> Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
Re-running some nightly testers w/ it enabled to verify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
951f699afb0872bec605a3d0e84c41cddcadf7b4 08-Sep-2010 Jim Grosbach <grosbach@apple.com> Fix errant fall-throughs causing the base pointer to be used when the frame
pointer was intended. rdar://8401980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
30c93e1cd3e43e174994834900325fcff3322288 08-Sep-2010 Jim Grosbach <grosbach@apple.com> Be more careful about when to do dynamic stack realignment. Since we have an
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6b53834d5fe1c51f3012f23ed9cbec267959e6bd 08-Sep-2010 Jim Grosbach <grosbach@apple.com> Add missing assert

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e1e6d187863ad7ca2e5331f496f27d480cb39734 08-Sep-2010 Jim Grosbach <grosbach@apple.com> disable for the moment while tracking down a few Thumb2-O0 failure that look
related. (attempt deux, complete w/ test update this time)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8b95dfe2b6c2c77b65bc35ce0db64d5a19617f29 08-Sep-2010 Jim Grosbach <grosbach@apple.com> woops. need to update a test along with this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8a076eb79db5f82729436938681e4787ebc4a305 08-Sep-2010 Jim Grosbach <grosbach@apple.com> disable temporarily while sorting out a few test failures in Thumb2-O0 tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113331 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
65482b1bb873dd820f54a24a2f34bd65f2669e5c 03-Sep-2010 Jim Grosbach <grosbach@apple.com> Re-apply r112883:
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."

r112986 fixed a latent bug exposed by the above.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
fc633002339439339e94f83eca9a012c6fc51e50 03-Sep-2010 Jim Grosbach <grosbach@apple.com> Check the local frame alignment for determining whether dynamic stack
alignment should be performed. Otherwise dynamic realignment may trigger
when the register allocator has already used the frame pointer as a general
purpose register. That is, we need to make sure that the list of reserved
registers doesn't change after register allocation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6a8700301ca6f8f2f5f787c8d1f5206a7dfceed6 03-Sep-2010 Daniel Dunbar <daniel@zuster.org> Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.

This reverts commit 8d6e29cfda270be483abf638850311670829ee65.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1755b3964f931bdd6fa9b4c0138f666ccfa12aca 03-Sep-2010 Jim Grosbach <grosbach@apple.com> For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.

rdar://7352504
rdar://8374540
rdar://8355680



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5c33f5bf67f61e3a1addda6de735d28d550dd0eb 02-Sep-2010 Jim Grosbach <grosbach@apple.com> trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112852 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c1dc78de762e8a65fe1edd0cced13d94ab5a971f 31-Aug-2010 Jim Grosbach <grosbach@apple.com> SP relative offsets need to be adjusted by the local allocation size when
determining if they're likely to be in range of the SP when resolving
frame references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d4511e947ee1e89a4f199bfac0d401976930ccfe 31-Aug-2010 Jim Grosbach <grosbach@apple.com> this assert should just be a condition, since this function is just asking if
the offset is legally encodable, not actually trying to do the encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
fcb4a8ead3cd8d9540d5eaa448af5d14a0ee341a 27-Aug-2010 Jim Grosbach <grosbach@apple.com> Simplify eliminateFrameIndex() interface back down now that PEI doesn't need
to try to re-use scavenged frame index reference registers. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1ab3f16f06698596716593a30545799688acccd7 26-Aug-2010 Jim Grosbach <grosbach@apple.com> tidy up a bit. no functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112228 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b0fa9932ccf9760e7b20ab4233799b4f9f5e0ba5 26-Aug-2010 Jim Grosbach <grosbach@apple.com> Turn off the scavenging based frame reg reuse briefly to measure whether it's
still having a significant effect. It shouldn't be now that the pre-RA
virtual base reg stuff is in. Assuming that's valididated by the nightly
testers, we can simplify a lot of the PEI frame index code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112220 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ae47c6d69e2e34bc558a302586cbc3f27a6d7334 26-Aug-2010 Jim Grosbach <grosbach@apple.com> Enable pre-RA virtual frame base register allocation. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f78ee6316bc755779920ac207edc27a89c0bd2f9 25-Aug-2010 Jim Grosbach <grosbach@apple.com> Don't override the var from the enclosing scope.

When doing copy/paste/modify, it's apparently rather important to remember
the 'modify' bit...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3197380143cdc18837722129ac888528b9fbfc2b 24-Aug-2010 Jim Grosbach <grosbach@apple.com> Add ARM heuristic for when to allocate a virtual base register for stack
access. rdar://8277890&7352504

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111968 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a273442891ae20fd8192526132e3819ea9e5eda9 24-Aug-2010 Jim Grosbach <grosbach@apple.com> Move enabling the local stack allocation pass into the target where it belongs.
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
cd59dc5e81eb080cd9b61f5a7e7d9f3eec206d8c 24-Aug-2010 Jim Grosbach <grosbach@apple.com> add ARM cmd line option to force always using virtual base regs when possible.
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e2f556933e1a19cddf6d4f370e2770c0f763b025 20-Aug-2010 Jim Grosbach <grosbach@apple.com> Better handling of offsets on frame index references. rdar://8277890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
74d7b0af58951dce2f874c600a6a48a2454b4914 19-Aug-2010 Jim Grosbach <grosbach@apple.com> Add Thumb1 support for virtual frame indices.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
2b1e202e1c2137b03f7c6ecc18668e40819fa22f 19-Aug-2010 Jim Grosbach <grosbach@apple.com> Enable ARM base register reuse to local stack slot allocation. Whenever a new
frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
74d803a58c7935c067397bb19afc05ec464d8159 18-Aug-2010 Jim Grosbach <grosbach@apple.com> Add hook for re-using virtual base registers for local stack slot access.
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
dc140c6e7b8350ca51aa1d408c10e25a27826e2c 18-Aug-2010 Jim Grosbach <grosbach@apple.com> Add materialization of virtual base registers for frame indices allocated into
the local block. Resolve references to those indices to a new base register.
For simplification and testing purposes, a new virtual base register is
allocated for each frame index being resolved. The result is truly horrible,
but correct, code that's good for exercising the new code paths.

Next up is adding thumb1 support, which should be very simple. Following that
will be adding base register re-use and implementing a reasonable ARM
heuristic for when a virtual base register should be generated at all.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8708ead5a46f4ec8f2d5f832be23381924d72b8d 17-Aug-2010 Jim Grosbach <grosbach@apple.com> Add hook to examine an instruction referencing a frame index to determine
whether to allocate a virtual frame base register to resolve the frame
index reference in it. Implement a simple version for ARM to aid debugging.

In LocalStackSlotAllocation, scan the function for frame index references
to local frame indices and ask the target whether to allocate virtual
frame base registers for any it encounters. Purely infrastructural for
debug output. Next step is to actually allocate base registers, then add
intelligent re-use of them.

rdar://8277890



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ac096808a3accc516ae7c193c9a2c1392bf3301a 10-Aug-2010 Evan Cheng <evan.cheng@apple.com> Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object.

Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110707 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4bd828f78139b9bab561102c5b9c40133ad375ca 10-Aug-2010 Daniel Dunbar <daniel@zuster.org> Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP
register is", it breaks a couple test-suite tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c9aed19747608b7688a64f2f382a008889f8e57d 10-Aug-2010 Evan Cheng <evan.cheng@apple.com> Fix ARM hasFP() semantics. It should return true whenever FP register is
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b000d683c822bab7bed608937048b24b4b6db551 10-Aug-2010 Evan Cheng <evan.cheng@apple.com> ARMBaseRegisterInfo::hasFP() has been broken for a while now. :-(
This will always be false before PEI:
(DisableFramePointerElim(MF) && MFI->adjustsStack())
Which means it's going to make r11 available as a general purpose register even
if -disable-fp-elim is specified. It's working on Darwin only because r7 is
always reserved. But it's obviously broken for other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110614 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e3ede5e2e4de6d028956c0b75c6bfa17ec50cc09 05-Aug-2010 Jim Grosbach <grosbach@apple.com> For local variables in functions with a frame pointer, use FP as a base
register for local access when it's closer to the stack slot being refererenced
than the stack pointer. Make sure to take into account any argument frame
SP adjustments that are in affect at the time.

rdar://8256090


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a7da3ac14ab1ca6da52547baf572d29c066559cc 05-Aug-2010 Chandler Carruth <chandlerc@gmail.com> Silence a GCC warning about && and || without explicit parentheses. This
preserves the existing behavior, as it seems a concious choice to allow RS to
be null and BigStack marked true.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
abf7bdffd67689781a5104b13fa806b92f3e96e1 05-Aug-2010 Jim Grosbach <grosbach@apple.com> and back in. false alarm on the tests from another unrelated local change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110269 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
87c0175cce653ee1d69d1efce77e7531c3066dac 05-Aug-2010 Jim Grosbach <grosbach@apple.com> oops. revert for a moment to clean up tests first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
936ed5424cc55a01cb6afdf687a82b134356ddc8 05-Aug-2010 Jim Grosbach <grosbach@apple.com> Reserve a stack slot if the function adjusts the stack but doesn't
simplify the call frame pseudo instructions. In that situation, the
calculations for estimating the stack size will be way off, leading to
not having an emergency spill slot when we need one. It should be possible
to be more precise about tracking the adjustment values, but not really
necessary for correctness. Upcoming cleanups for PEI in general will
render that moot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110258 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d1fb583128c6682bb8a7c74eafa810a9270cc8df 03-Aug-2010 Nate Begeman <natebegeman@mac.com> Add support for getting & setting the FPSCR application register on ARM when VFP is enabled.
Add support for using the FPSCR in conjunction with the vcvtr instruction, for controlling fp to int rounding.
Add support for the FLT_ROUNDS_ node now that the FPSCR is exposed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1c55386dae428d076bd7d054ed8bbb59c4ba954e 22-Jul-2010 Chris Lattner <sabre@nondot.org> switch a private implementation of GetFunctionSizeInBytes.
This is probably not the best way to implement "Force LR to
be spilled if the Thumb function size is > 2048." do this,
it should use the branch shortening infrastructure, but I'm
just preserving functionality here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
72852a8cfb605056d87b644d2e36b1346051413d 20-Jul-2010 Eric Christopher <echristo@apple.com> Constify some arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108812 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
697cba8ec2b3f5160175fd5b4a641dbd48606e17 17-Jul-2010 Eric Christopher <echristo@apple.com> Remove unnecessary check that was subsumed into canRealignStack.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d4c36cec1db81b4ee48cd4ab462262615d78f22c 17-Jul-2010 Eric Christopher <echristo@apple.com> Make more explicit and add some currently disabled error messages for
stack realignment on ARM.

Also check for function attributes as we do on X86 as well as
make explicit that we're checking can as well as needs in this function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
68eec39bca280f98bef1256a5e89531ac1a77d1a 10-Jul-2010 Chandler Carruth <chandlerc@gmail.com> Add parentheses yet again to satisfy GCC's warnings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6c7d3a16b3321c527e35322e869c73d47dba719d 09-Jul-2010 Jim Grosbach <grosbach@apple.com> In the presence of variable sized objects, allocate an emergency spill slot.
rdar://8131327

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7835f1fcdbb58093377c9e3476f45a2638565762 08-Jul-2010 Dale Johannesen <dalej@apple.com> Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
52c61ec1640a9fa1cf8c2fde97a14dfbf5e702b7 18-Jun-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
10416803c1370fe1e52a7f1c431fe506be9c1ef5 18-Jun-2010 Dale Johannesen <dalej@apple.com> An attempt to fix the problem Anton reported with
ARM tail calls. Don't know if it works, but it
doesn't break Darwin.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6470a116f17b70aba0c2e7ee751551a5ac9797f6 16-Jun-2010 Dale Johannesen <dalej@apple.com> Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this. Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106053 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
51e28e634880849ed9f7c02e93c08d25dd70291b 03-Jun-2010 Dale Johannesen <dalej@apple.com> Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
91a74da036d3a9442953ae1de3e797a50da4ccf0 02-Jun-2010 Bob Wilson <bob.wilson@apple.com> Rename canCombinedSubRegIndex method to something more grammatically correct
and tidy up the comment describing it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
20fae651816916000c47b78843f22fd259ba4216 02-Jun-2010 Rafael Espindola <rafael.espindola@gmail.com> Replace ARM's getCalleeSavedRegClasses with a simpler solution

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e00fa64c16f40230d76417be8f09166b7c84c52d 25-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Use enums instead of literals in the ARM backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
558661d2718cf5750907c449d36ff1231924a2d1 24-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums
from ARMRegisterInfo.h

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104508 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
535af4a320ba169342c87433841dc64fbdcd72b3 18-May-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
too large limit.

The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.

A test case is very difficult to produce because it will only fail when the
scavenger is used.

rdar://problem/7894847

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b990a2f249196ad3e0cc451d40a45fc2f9278eaf 15-May-2010 Evan Cheng <evan.cheng@apple.com> Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE
instructions.

e.g.
%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1027<def> = EXTRACT_SUBREG %reg1026, 6
%reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5
...
%reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12

After REG_SEQUENCE is eliminated, we are left with:

%reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0
%reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6
%reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5

The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't
know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the
target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger
sub-register (or combined to be reg1026 itself as is the case here). If it is possible,
it will be able to replace references of reg1026 with reg1029 + the larger sub-register
index.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b92187a4103dca24c3767c380f63593d1f6161a7 14-May-2010 Bill Wendling <isanbard@gmail.com> Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what
the variable actually tracks.

N.B., several back-ends are using "HasCalls" as being synonymous for something
that adjusts the stack. This isn't 100% correct and should be looked into.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
22c687b6421d9cc03351ddb0c7fd3d45382bc01a 14-May-2010 Evan Cheng <evan.cheng@apple.com> Added a QQQQ register file to model 4-consecutive Q registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1190c14b547a1e275e80e43a6ad52178312adbd7 13-May-2010 Bob Wilson <bob.wilson@apple.com> Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.
Do not use those for Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b63387afc6b10e88631d1ef232c41ab6c18c8581 06-May-2010 Evan Cheng <evan.cheng@apple.com> Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f865cb5c1f00d5655d981503ed5761b2836fa5a8 06-May-2010 Eric Christopher <echristo@apple.com> Revert r103156 since it was breaking the build bots.

Reverse-merging r103156 into '.':
U lib/Target/ARM/ARMInstrNEON.td
U lib/Target/ARM/ARMRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
U lib/Target/ARM/ARMBaseInstrInfo.cpp
U lib/Target/ARM/ARMRegisterInfo.td



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4ffc22ae000f207d3c660ebc197d31940025fbfa 06-May-2010 Evan Cheng <evan.cheng@apple.com> Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
62b50656ceb854eb0be265d63b2a1d46e7400d8a 26-Apr-2010 Evan Cheng <evan.cheng@apple.com> Add ARM specific emitFrameIndexDebugValue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e566763b1915c7a4821ce95937b763724d271fec 21-Apr-2010 Evan Cheng <evan.cheng@apple.com> Implement -disable-non-leaf-fp-elim which disable frame pointer elimination
optimization for non-leaf functions. This will be hooked up to gcc's
-momit-leaf-frame-pointer option. rdar://7886181


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8c407d45964fbba19719be555324f247e4fb14e1 15-Apr-2010 Dan Gohman <gohman@apple.com> ReuseFrameIndexVals is used in multiple files, so it can't be static.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b35798347ea87b8b6d36155b211016a7769f01ab 15-Apr-2010 Dan Gohman <gohman@apple.com> Fix a bunch of namespace polution.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
46510a73e977273ec67747eb34cbdb43f815e451 15-Apr-2010 Dan Gohman <gohman@apple.com> Add const qualifiers to CodeGen's use of LLVM IR constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c7f3ace20c325521c68335a1689645b43b06ddf0 02-Apr-2010 Chris Lattner <sabre@nondot.org> use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
98330ff8e344d2e88c0a2166901d394e813e8162 20-Mar-2010 Bob Wilson <bob.wilson@apple.com> Fix a very bad typo. Since the register number was off by one, the ARM
load/store optimizer would incorrectly think that registers D26 and D28
were consecutive and would generate a VLDM instruction to load them.
The assembler was not convinced.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f49be7c96f5a57ba67e6b1dc4362273b5f7cbd81 10-Mar-2010 Jim Grosbach <grosbach@apple.com> Make sure the LR gets pushed in functions that use vaargs. This fixes
400.perlbench for the nightly tests.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
dff4b4c5a7cc894d3b4b6c6e779ea8f47fa50630 09-Mar-2010 Jim Grosbach <grosbach@apple.com> Change the Value argument to eliminateFrameIndex to a type-tagged value. This
is preparatory to having PEI's scavenged frame index value reuse logic
properly distinguish types of frame values (e.g., whether the value is
stack-pointer relative or frame-pointer relative).

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98086 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4e501545cd12d903d35096f42eb5fdbe4603d5da 09-Mar-2010 Jim Grosbach <grosbach@apple.com> scavenged frame index value re-use gets confused when more than one base
register is involved for thumb1. Work around this for the moment by only
re-using SP-relative offsets. This is temporary 'til the code can distinguish
multiple base registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
436e6e7b5c85f12b7c2e41b7fd5c48e5d4d72912 04-Mar-2010 Bob Wilson <bob.wilson@apple.com> pr6478: The frame pointer spill frame index is only defined when there is a
frame pointer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
657baec0af38d84e24e4738b0696bb99d1517179 24-Feb-2010 Jakob Stoklund Olesen <stoklund@2pi.dk> Create a stack frame on ARM when

- Function uses all scratch registers AND
- Function does not use any callee saved registers AND
- Stack size is too big to address with immediate offsets.

In this case a register must be scavenged to calculate the address of a stack
object, and the scavenger needs a spare register or emergency spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97071 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ff28103b192a7e818f92628c2a4e34e622c1a142 24-Feb-2010 Chandler Carruth <chandlerc@gmail.com> Remove an unused variable. Was this intentional?


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5f366af2ff36cc65fe4964194b07bf1455828ff0 24-Feb-2010 Jim Grosbach <grosbach@apple.com> handle very large call frames when require SPAdj != 0 for Thumb1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
cf453ee70a1ae03cc641686fd5db0f8a7d8ce250 23-Feb-2010 Jim Grosbach <grosbach@apple.com> Spelling. s/suppor /support /

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4642ad3af1cf508ac320b9afd25b065f08b36574 23-Feb-2010 Jim Grosbach <grosbach@apple.com> Updated version of r96634 (which was reverted due to failing 176.gcc and
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5a0815fae849038c0f125d04ea948785f52d35cc 22-Feb-2010 Jim Grosbach <grosbach@apple.com> Clean up a bit and fix for when SPAdj != 0

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96818 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4c7628e43d8468f215ea345545479b6d728cee92 22-Feb-2010 Jim Grosbach <grosbach@apple.com> The predicate index isn't fixed, so scan for it to make sure we get the proper
value.

Thumb2 uses the tADJCALLSTACK* instructions, and doesn't need t2 versions, so
remove the FIXME entry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96817 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1a2e8686f8137a1a2329952ffd1e21969ea1658c 19-Feb-2010 Bob Wilson <bob.wilson@apple.com> Revert 96634. It causes assertion failures for 126.gcc and 176.gcc in
the armv6 nightly tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
cf43e60544041c127bb875fe4cf0d0ae96cd6c78 19-Feb-2010 Jim Grosbach <grosbach@apple.com> Radar 7636153. In the presence of large call frames, it's not sufficient
for ARM to just check if a function has a FP to determine if it's safe
to simplify the stack adjustment pseudo ops prior to eliminating frame
indices. Allow targets to override the default behavior and does so for ARM
and Thumb2.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7545f49a5edfe19612d03e683d8b955c03018056 13-Feb-2010 Evan Cheng <evan.cheng@apple.com> Teach MachineFrameInfo to track maximum alignment while stack objects are being
created. This ensures it's updated at all time. It means targets which perform
dynamic stack alignment would know whether it is required and whether frame
pointer register cannot be made available register allocation.
This is a fix for rdar://7625239. Sorry, I can't create a reasonably sized test
case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
985d45dea357cbfe718b89cebd84b20b1298ab93 03-Feb-2010 Jim Grosbach <grosbach@apple.com> As of r79039, we still try to eliminate the frame pointer on leaf functions,
even when -disable-fp-elim is specified.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95161 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
30c6b75ac2eef548c18110a38c9798ea5314caba 27-Jan-2010 Chris Lattner <sabre@nondot.org> constify a method argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e45ab8a0a90e4f3a59d8c38038ae3e495ee1fef3 19-Jan-2010 Jim Grosbach <grosbach@apple.com> For aligned load/store instructions, it's only required to know whether a
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
9631864688c593711f82bb8d21f8b724c628d786 07-Jan-2010 Jim Grosbach <grosbach@apple.com> 80 column violations

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92876 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ce3e769c15be90463abf14bb71b5a8e1205d3661 07-Jan-2010 Jim Grosbach <grosbach@apple.com> Addressing mode 6 (load/store) instructions can't encode an immediate offset
for stack references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e9912dc553bf7e37494eb9b07e8ff880f0481a56 22-Dec-2009 Jakob Stoklund Olesen <stoklund@2pi.dk> Use proper move instructions. Make the verifier happy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7cca606aaa6fee6ff4f548aa3686608b6be1f208 06-Dec-2009 Anton Korobeynikov <asl@math.spbu.ru> Dynamic stack realignment use of sp register as source/dest register
in "bic sp, sp, #15" leads to unpredicatble behaviour in Thumb2 mode.
Emit the following code instead:
mov r4, sp
bic r4, r4, #15
mov sp, r4

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e27d205d5d4d53cceabcd6325533fbdf9c0cee42 02-Dec-2009 Jim Grosbach <grosbach@apple.com> Factor the stack alignment calculations out into a target independent pass.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a37aa546224ec03ba1f1a1598e0781af4b692673 22-Nov-2009 Jim Grosbach <grosbach@apple.com> Move default FrameReg val to getFrameIndexReference(). Otherwise, debug info can get bogus values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
50f8516d2dd87e6c02a46fa349b75101f9db8619 22-Nov-2009 Jim Grosbach <grosbach@apple.com> Generate more correct debug info for frame indices.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89576 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
21ce2e3c74d3b64a9dafde190d18dbf3aa003112 22-Nov-2009 Jim Grosbach <grosbach@apple.com> Revert 89562. We're being sneakier than I was giving us credit for, and this
isn't necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f3b33d0b2a50777ddb467e8adefbb018b16570d2 21-Nov-2009 Jim Grosbach <grosbach@apple.com> Darwin requires a frame pointer for all non-leaf functions to support correct
backtraces.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7bde2971330d8d64d6650d002db9c1ce77f4e4d4 16-Nov-2009 Jim Grosbach <grosbach@apple.com> Make the pass class name more explicit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
074fb0252d20dfc4b03bc902b94e11d9cd8592d8 16-Nov-2009 Jim Grosbach <grosbach@apple.com> make pass name a bit more clear

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a44321776ecd96fa0344335d3027758be3386e45 15-Nov-2009 Jim Grosbach <grosbach@apple.com> Detect need for autoalignment of the stack earlier to catch spills more
conservatively. eliminateFrameIndex() machinery adjust to handle addr mode
6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3f2bf85d14759cc4b28a86805f566ac805a54d00 12-Nov-2009 David Greene <greened@obbligato.org> Add a bool flag to StackObjects telling whether they reference spill
slots. The AsmPrinter will use this information to determine whether to
print a spill/reload comment.

Remove default argument values. It's too easy to pass a wrong argument
value when multiple arguments have default values. Make everything
explicit to trap bugs early.

Update all targets to adhere to the new interfaces..


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@87022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
803b48a155eb2b3f9fe3823ecd7cbbd0089b2809 10-Nov-2009 Jim Grosbach <grosbach@apple.com> Now that the default is 'enabled,' a separate command line option for ARM is
not necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
92eb919e807c2c7ba5c5cde131a340ea0a77f94b 09-Nov-2009 Jim Grosbach <grosbach@apple.com> Enable dynamic stack realignment by default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ad353c74adda55556f7a3969721c3e49ac16d570 09-Nov-2009 Jim Grosbach <grosbach@apple.com> Set dynamic stack realignment to real values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5 09-Nov-2009 Jim Grosbach <grosbach@apple.com> Use Unified Assembly Syntax for the ARM backend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
31bc849123011b8eae6bb3c79876d9a3c26a6a1d 08-Nov-2009 Jim Grosbach <grosbach@apple.com> Use aligned load/store instructions for spilling Q registers when we know the stack slot is 128 bit aligned

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4371cda7f8fc21fc3192ead122ba48b0152fb0e4 05-Nov-2009 Jim Grosbach <grosbach@apple.com> Grammar.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
db1751a9222dbfc62e6d7c2ec0b084d353068931 05-Nov-2009 Jim Grosbach <grosbach@apple.com> Now that the memory leak from McCat/08-main has been fixed (86056), re-enable
aggressive testing of dynamic stack alignment.
Note that this is off by default, and enabled for LLCBETA nightly results.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6db06a0866cd36fec05e6d9afb357ce8efb575e9 04-Nov-2009 Jim Grosbach <grosbach@apple.com> If a function has no stack frame at all, dynamic realignment isn't necessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c5848f4ced8f9174e7141c0d2589acaafa13ff35 04-Nov-2009 Jim Grosbach <grosbach@apple.com> dynamic stack realignment necessitates scanning the floating point callee-
saved instructions even if no stack adjustment for those saves is needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86056 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ba908640b3e0c1218748776e244d4b7234451155 03-Nov-2009 Evan Cheng <evan.cheng@apple.com> Fix PR5367. QPR_8 is the super regclass of DPR_8 and SPR_8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ab453e06418cceabc909527dcf38a4914ef61f77 03-Nov-2009 Anton Korobeynikov <asl@math.spbu.ru> Revert r85049, it is causing PR5367

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
48d8afab73d72418cf9505a020f621014920463c 01-Nov-2009 Evan Cheng <evan.cheng@apple.com> Make use of imm12 version of Thumb2 ldr / str instructions more aggressively.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
95d9504d46a18d65facca9a86cd53fa03cba1eca 30-Oct-2009 Jim Grosbach <grosbach@apple.com> Dial back the realignment a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85546 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
84e58d03c910aa6ea8557d2f2f9de1f96162cae1 29-Oct-2009 Jim Grosbach <grosbach@apple.com> To get more thorough testing from llc-beta nightly runs, do dynamic stack
realignment regardless of whether it's strictly necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ca5dfb71ba4aa4a8392a021ec056cf0b70f74f1e 28-Oct-2009 Jim Grosbach <grosbach@apple.com> Cleanup now that frame index scavenging via post-pass is working for ARM and Thumb2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a6a99b4e160eea0060b25fbdeadc3437cd67d617 27-Oct-2009 Jim Grosbach <grosbach@apple.com> Enable virtual register based frame index scavenging by default for ARM & T2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3dab2778571b5bb00b35a0adcb7011dc85158beb 27-Oct-2009 Jim Grosbach <grosbach@apple.com> Infrastructure for dynamic stack realignment on ARM. For now, this is off by
default behind a command line option. This will enable better performance for
vectors on NEON enabled processors.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
4f54c1293af174a8002db20faf7b4f82ba4e8514 25-Oct-2009 Evan Cheng <evan.cheng@apple.com> Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
41fff8c19ab6d8e28f5362481c184ad628f8c704 22-Oct-2009 Jim Grosbach <grosbach@apple.com> Missing piece of the ARM frame index post-scavenging conditionalization

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1d6827bbe947730cb91d68a9fd9c469f7f56a6ae 22-Oct-2009 Jim Grosbach <grosbach@apple.com> Conditionalize ARM/T2 frame index post-scavenging while working out fixes
for a few bugs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3229b0bcf1fe5e9381f306ed30c37cec0377395a 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Disable by default while debugging

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84669 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
18ed9c9a2bd7f1f56129495b499264c58b5cc4f4 20-Oct-2009 Jim Grosbach <grosbach@apple.com> add cmd line opt to disable frame index reuse for ARM and T2. debug aid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
7e831db1d4f5dc51ca6526739cf41e59895c5c20 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Enable post-pass frame index register scavenging for ARM and Thumb2

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84585 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6009751244909c277e6cee8e74a4ccf1846953bc 20-Oct-2009 Jim Grosbach <grosbach@apple.com> Enable allocation of R3 in Thumb1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b58f498f7502e7e1833decbbbb4df771367c7341 07-Oct-2009 Jim Grosbach <grosbach@apple.com> Add register-reuse to frame-index register scavenging. When a target uses
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
540b05d227a79443b2a7b07d5152a35cb6392abf 06-Oct-2009 Jim Grosbach <grosbach@apple.com> In Thumb1, the register scavenger is not always able to use an emergency
spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
460c482ed38f5c2f91e29eaacf241928d3d77edf 30-Sep-2009 Jim Grosbach <grosbach@apple.com> Clarify comment phrasing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83148 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
d1a5ca6cb11763059ba1ee1c965cc69abff92e38 30-Sep-2009 Jim Grosbach <grosbach@apple.com> When checking whether we need to reserve a register for the scavenger,
the size of the saved frame pointer needs to be taken into account.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
17487ba60d171aa32b17e6c3ad6d5809e78f9868 30-Sep-2009 Jim Grosbach <grosbach@apple.com> minor cleanup and add clarifying comment

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83117 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ec9eef4a15157fc0a05feff933848aa9283bd1af 29-Sep-2009 Jim Grosbach <grosbach@apple.com> Adjust processFunctionBeforeCalleeSavedScan() to correctly reserve a stack
slot for the register scavenger when compiling Thumb1 functions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c8ce2d4cb9ef5ff8b3c574e522c870741d88ba58 25-Sep-2009 Bob Wilson <bob.wilson@apple.com> Add some comments to clarify things that I discovered this week.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
3d6cb88a64fe67064de206405951eb326d86fc0c 25-Sep-2009 Jim Grosbach <grosbach@apple.com> Start of revamping the register scavenging in PEI. ARM Thumb1 is the driving
interest for this, as it currently reserves a register rather than using
the scavenger for matierializing constants as needed.

Instead of scavenging registers on the fly while eliminating frame indices,
new virtual registers are created, and then a scavenged collectively in a
post-pass over the function. This isolates the bits that need to interact
with the scavenger, and sets the stage for more intelligent use, and reuse,
of scavenged registers.

For the time being, this is disabled by default. Once the bugs are worked out,
the current scavenging calls in replaceFrameIndices() will be removed and
the post-pass scavenging will be the default. Until then,
-enable-frame-index-scavenging enables the new code. Currently, only the
Thumb1 back end is set up to use it.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
a15de00f8246f19180b26ee5fe7ff8f436e0de08 18-Sep-2009 Bob Wilson <bob.wilson@apple.com> Fix a typo in an assertion message.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
82b3c2e40417098f9af0c33150c4b1c66ae1747c 11-Sep-2009 Jim Grosbach <grosbach@apple.com> Revert array initialization regclass change so that the initialization stays static, not runtime.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e11a8f565c6a019ddc54667227be9c4d8f117473 11-Sep-2009 Jim Grosbach <grosbach@apple.com> Update register class references to use the global constant ARM::*RegisterClass names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
19bb87d0f80f3e6eed38a9fa267bf2b0474aeaab 28-Aug-2009 Daniel Dunbar <daniel@zuster.org> Fix -Asserts warning, round two.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ca7943226e1d58f4f3ae936f93aa03c2a72289ae 28-Aug-2009 Daniel Dunbar <daniel@zuster.org> Fix -Asserts warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
cdbb3f5d3311e0f46d22bc8daa211b2fab3541cb 27-Aug-2009 Evan Cheng <evan.cheng@apple.com> Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c0823fe7c679ca8f7d1667a310c2fca97b9402d5 18-Aug-2009 Jakob Stoklund Olesen <stoklund@2pi.dk> Simplify RegScavenger::FindUnusedReg.

- Drop the Candidates argument and fix all callers. Now that RegScavenger
tracks available registers accurately, there is no need to restict the
search.
- Make sure that no aliases of the found register are in use. This was a potential bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
010b1b9e7b11bced0b277a4d808226ba2af3044a 15-Aug-2009 Evan Cheng <evan.cheng@apple.com> Do not use frame register to reference fixed stack objects if the function is frameless.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
98a0104014e9bb6ed89c2572f615351fd526674a 14-Aug-2009 Evan Cheng <evan.cheng@apple.com> Leaf functions which do not save CSRs can be frameless even with -disable-fp-elim.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79039 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
1d0be15f89cb5056e20e2d24faa8d6afb1573bca 13-Aug-2009 Owen Anderson <resistor@mac.com> Push LLVMContexts through the IntegerType APIs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
764ab52dd80310a205c9888bf166d09dab858f90 11-Aug-2009 Jim Grosbach <grosbach@apple.com> Whitespace cleanup. Remove trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
052053bbe3169a3574cb5af026cf0a5d616ae04d 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> Use tMOVgpr2gpr instead of t2MOVr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
861986401e05e437cb33bfd8320d510b956fe41e 07-Aug-2009 Evan Cheng <evan.cheng@apple.com> It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.

This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.

This fixes PR4659 and PR4682.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78361 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ee42fd309ee6a8febfafb97c2f3b6f2069758c5e 31-Jul-2009 Evan Cheng <evan.cheng@apple.com> When fp is not eliminated, instructions with T2_i12 modes will be changed to T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
2cfd52c507bd5790457a171eb9bcb39019cc6860 29-Jul-2009 Chris Lattner <sabre@nondot.org> Give getPointerRegClass() a "kind" value so that targets can
support multiple different pointer register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b180d992d81f97862af6089dfe899d0363cac6f5 28-Jul-2009 Chris Lattner <sabre@nondot.org> more simplifications and cleanup. :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
542383d93b146e11a1d70c01f8afea8ea9f08eff 28-Jul-2009 Evan Cheng <evan.cheng@apple.com> Code clean up. No functionality changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
6495f63945e8dbde81f03a1dc2ab421993b9a495 28-Jul-2009 Evan Cheng <evan.cheng@apple.com> - More refactoring. This gets rid of all of the getOpcode calls.
- This change also makes it possible to switch between ARM / Thumb on a
per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
fc17fb0aeed584b8560461ab2843d0676a243f29 27-Jul-2009 Evan Cheng <evan.cheng@apple.com> Get rid of more dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77227 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
293f8d9b8800ab68c64b67f38a7f76e00126715d 27-Jul-2009 Evan Cheng <evan.cheng@apple.com> Cosmetic change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5ca53a7ad821613d324e4189ddbb0d468a326146 27-Jul-2009 Evan Cheng <evan.cheng@apple.com> Get rid of some more getOpcode calls.

This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5732ca084aaa0cd26149e50dd4b487efff37fe41 27-Jul-2009 Evan Cheng <evan.cheng@apple.com> Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate more getOpcode calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77181 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
30b2bdfa734d59bb7bc769dc2f06e4900a77f6f8 26-Jul-2009 Evan Cheng <evan.cheng@apple.com> Refactor. Get rid of a few more getOpcode() calls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c7423aff68630d7fd1250337505a8e4be09d0f15 25-Jul-2009 Evan Cheng <evan.cheng@apple.com> 80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
eed707b1e6097aac2bb6b3d47271f6300ace7f2e 25-Jul-2009 Owen Anderson <resistor@mac.com> Revert the ConstantInt constructors back to their 2.5 forms where possible, thanks to contexts-on-types. More to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b74bb1a7a471a77e793d90de158aa4bbc67fe94d 24-Jul-2009 Evan Cheng <evan.cheng@apple.com> FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same instructions on all sub-targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
5ff58b5c3ab6df332600678798ea5c69c5e943d3 24-Jul-2009 David Goodwin <david_goodwin@apple.com> Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index elimination more exactly for Thumb-2 to get better code gen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76919 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
b53cc014d0f47b898c9daca34566c16dda6c4c1e 23-Jul-2009 David Goodwin <david_goodwin@apple.com> Fix frame index elimination to correctly handle thumb-2 addressing modes that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
697712c7d42cbd30fe07367abdbfa0620666e3a3 23-Jul-2009 Evan Cheng <evan.cheng@apple.com> 80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8295d99bff6f8e3dfdfdaf1871cb72adab423f20 22-Jul-2009 Evan Cheng <evan.cheng@apple.com> Get rid one of the getRegisterNumbering. Also add D16 - D31.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76725 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e922c0201916e0b980ab3cfe91e1413e68d55647 22-Jul-2009 Owen Anderson <resistor@mac.com> Get rid of the Pass+Context magic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
378445303b10b092a898a75131141a8259cff50b 16-Jul-2009 Evan Cheng <evan.cheng@apple.com> Let callers decide the sub-register index on the def operand of rematerialized instructions.
Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
9adc0abad3c3ed40a268ccbcee0c74cb9e1359fe 15-Jul-2009 Owen Anderson <resistor@mac.com> Move EVER MORE stuff over to LLVMContext.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c23197a26f34f559ea9797de51e187087c039c42 14-Jul-2009 Torok Edwin <edwintorok@gmail.com> llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ea670f1dd8067a9b65f952d0548669045bf0e21f 13-Jul-2009 David Goodwin <david_goodwin@apple.com> Fix FP elimination code to work for Thumb-2 addrmode AddrModeT2_so. This fixes SingleSource/Benchmarks/Stanford/Queens (among others).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75513 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c25e7581b9b8088910da31702d4ca21c4734c6d7 11-Jul-2009 Torok Edwin <edwintorok@gmail.com> assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
446c428bf394b7113b0f18cbacb5e87b4efd1e14 11-Jul-2009 Evan Cheng <evan.cheng@apple.com> Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.

A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75359 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
8b98b85c64543e7ec479f40e5c2b5a24aa862fed 09-Jul-2009 David Goodwin <david_goodwin@apple.com> Handle Thumb-2 addressing modes during FP elimination.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
f1daf7d8abebd6e0104a6b41a774ccbb19a51c60 09-Jul-2009 David Goodwin <david_goodwin@apple.com> Use common code for both ARM and Thumb-2 instruction and register info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
e7cbe4118b7ddf05032ff8772a98c51e1637bb5c 08-Jul-2009 Evan Cheng <evan.cheng@apple.com> Change how so_imm and t2_so_imm are handled. At instruction selection time, the immediates are no longer encoded in the imm8 + rot format, that are left as it is. The encoding is now done in ams printing and code emission time instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
dac237e18209b697a8ba122d0ddd9cad4dfba1f8 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Implement changes from Chris's feedback.
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
77521f5232e679aa3de10aaaed2464aa91d7ff55 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Generalize opcode selection in ARMBaseRegisterInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
db5a71a8e01ed9a0d93a19176df6ea0aea510d7b 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Push methods into base class in preparation for sharing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
ab7c09b6b6f4516a631fd6788918c237c83939af 08-Jul-2009 Torok Edwin <edwintorok@gmail.com> Start converting to new error handling API.
cerr+abort -> llvm_report_error
assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
c140c4803dc3e10e08138670829bc0494986abe9 08-Jul-2009 David Goodwin <david_goodwin@apple.com> Start breaking out common base functionality for register info.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp