ARMBaseRegisterInfo.cpp revision d0c38176690e9602a93a20a43f1bd084564a8116 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42using namespace llvm;
43
44static cl::opt<bool>
45ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
46          cl::desc("Force use of virtual base registers for stack load/store"));
47static cl::opt<bool>
48EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
49          cl::desc("Enable pre-regalloc stack frame index allocation"));
50static cl::opt<bool>
51EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
52          cl::desc("Enable use of a base pointer for complex stack frames"));
53
54ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
55                                         const ARMSubtarget &sti)
56  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
57    TII(tii), STI(sti),
58    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
59    BasePtr(ARM::R6) {
60}
61
62const unsigned*
63ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
64  static const unsigned CalleeSavedRegs[] = {
65    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
66    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
67
68    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
69    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
70    0
71  };
72
73  static const unsigned DarwinCalleeSavedRegs[] = {
74    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
75    // register.
76    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
77    ARM::R11, ARM::R10, ARM::R8,
78
79    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
80    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
81    0
82  };
83  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
84}
85
86BitVector ARMBaseRegisterInfo::
87getReservedRegs(const MachineFunction &MF) const {
88  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
89
90  // FIXME: avoid re-calculating this everytime.
91  BitVector Reserved(getNumRegs());
92  Reserved.set(ARM::SP);
93  Reserved.set(ARM::PC);
94  Reserved.set(ARM::FPSCR);
95  if (TFI->hasFP(MF))
96    Reserved.set(FramePtr);
97  if (hasBasePointer(MF))
98    Reserved.set(BasePtr);
99  // Some targets reserve R9.
100  if (STI.isR9Reserved())
101    Reserved.set(ARM::R9);
102  return Reserved;
103}
104
105bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
106                                        unsigned Reg) const {
107  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
108
109  switch (Reg) {
110  default: break;
111  case ARM::SP:
112  case ARM::PC:
113    return true;
114  case ARM::R6:
115    if (hasBasePointer(MF))
116      return true;
117    break;
118  case ARM::R7:
119  case ARM::R11:
120    if (FramePtr == Reg && TFI->hasFP(MF))
121      return true;
122    break;
123  case ARM::R9:
124    return STI.isR9Reserved();
125  }
126
127  return false;
128}
129
130const TargetRegisterClass *
131ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
132                                              const TargetRegisterClass *B,
133                                              unsigned SubIdx) const {
134  switch (SubIdx) {
135  default: return 0;
136  case ARM::ssub_0:
137  case ARM::ssub_1:
138  case ARM::ssub_2:
139  case ARM::ssub_3: {
140    // S sub-registers.
141    if (A->getSize() == 8) {
142      if (B == &ARM::SPR_8RegClass)
143        return &ARM::DPR_8RegClass;
144      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
145      if (A == &ARM::DPR_8RegClass)
146        return A;
147      return &ARM::DPR_VFP2RegClass;
148    }
149
150    if (A->getSize() == 16) {
151      if (B == &ARM::SPR_8RegClass)
152        return &ARM::QPR_8RegClass;
153      return &ARM::QPR_VFP2RegClass;
154    }
155
156    if (A->getSize() == 32) {
157      if (B == &ARM::SPR_8RegClass)
158        return 0;  // Do not allow coalescing!
159      return &ARM::QQPR_VFP2RegClass;
160    }
161
162    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
163    return 0;  // Do not allow coalescing!
164  }
165  case ARM::dsub_0:
166  case ARM::dsub_1:
167  case ARM::dsub_2:
168  case ARM::dsub_3: {
169    // D sub-registers.
170    if (A->getSize() == 16) {
171      if (B == &ARM::DPR_VFP2RegClass)
172        return &ARM::QPR_VFP2RegClass;
173      if (B == &ARM::DPR_8RegClass)
174        return 0;  // Do not allow coalescing!
175      return A;
176    }
177
178    if (A->getSize() == 32) {
179      if (B == &ARM::DPR_VFP2RegClass)
180        return &ARM::QQPR_VFP2RegClass;
181      if (B == &ARM::DPR_8RegClass)
182        return 0;  // Do not allow coalescing!
183      return A;
184    }
185
186    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
187    if (B != &ARM::DPRRegClass)
188      return 0;  // Do not allow coalescing!
189    return A;
190  }
191  case ARM::dsub_4:
192  case ARM::dsub_5:
193  case ARM::dsub_6:
194  case ARM::dsub_7: {
195    // D sub-registers of QQQQ registers.
196    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
197      return A;
198    return 0;  // Do not allow coalescing!
199  }
200
201  case ARM::qsub_0:
202  case ARM::qsub_1: {
203    // Q sub-registers.
204    if (A->getSize() == 32) {
205      if (B == &ARM::QPR_VFP2RegClass)
206        return &ARM::QQPR_VFP2RegClass;
207      if (B == &ARM::QPR_8RegClass)
208        return 0;  // Do not allow coalescing!
209      return A;
210    }
211
212    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
213    if (B == &ARM::QPRRegClass)
214      return A;
215    return 0;  // Do not allow coalescing!
216  }
217  case ARM::qsub_2:
218  case ARM::qsub_3: {
219    // Q sub-registers of QQQQ registers.
220    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
221      return A;
222    return 0;  // Do not allow coalescing!
223  }
224  }
225  return 0;
226}
227
228bool
229ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
230                                          SmallVectorImpl<unsigned> &SubIndices,
231                                          unsigned &NewSubIdx) const {
232
233  unsigned Size = RC->getSize() * 8;
234  if (Size < 6)
235    return 0;
236
237  NewSubIdx = 0;  // Whole register.
238  unsigned NumRegs = SubIndices.size();
239  if (NumRegs == 8) {
240    // 8 D registers -> 1 QQQQ register.
241    return (Size == 512 &&
242            SubIndices[0] == ARM::dsub_0 &&
243            SubIndices[1] == ARM::dsub_1 &&
244            SubIndices[2] == ARM::dsub_2 &&
245            SubIndices[3] == ARM::dsub_3 &&
246            SubIndices[4] == ARM::dsub_4 &&
247            SubIndices[5] == ARM::dsub_5 &&
248            SubIndices[6] == ARM::dsub_6 &&
249            SubIndices[7] == ARM::dsub_7);
250  } else if (NumRegs == 4) {
251    if (SubIndices[0] == ARM::qsub_0) {
252      // 4 Q registers -> 1 QQQQ register.
253      return (Size == 512 &&
254              SubIndices[1] == ARM::qsub_1 &&
255              SubIndices[2] == ARM::qsub_2 &&
256              SubIndices[3] == ARM::qsub_3);
257    } else if (SubIndices[0] == ARM::dsub_0) {
258      // 4 D registers -> 1 QQ register.
259      if (Size >= 256 &&
260          SubIndices[1] == ARM::dsub_1 &&
261          SubIndices[2] == ARM::dsub_2 &&
262          SubIndices[3] == ARM::dsub_3) {
263        if (Size == 512)
264          NewSubIdx = ARM::qqsub_0;
265        return true;
266      }
267    } else if (SubIndices[0] == ARM::dsub_4) {
268      // 4 D registers -> 1 QQ register (2nd).
269      if (Size == 512 &&
270          SubIndices[1] == ARM::dsub_5 &&
271          SubIndices[2] == ARM::dsub_6 &&
272          SubIndices[3] == ARM::dsub_7) {
273        NewSubIdx = ARM::qqsub_1;
274        return true;
275      }
276    } else if (SubIndices[0] == ARM::ssub_0) {
277      // 4 S registers -> 1 Q register.
278      if (Size >= 128 &&
279          SubIndices[1] == ARM::ssub_1 &&
280          SubIndices[2] == ARM::ssub_2 &&
281          SubIndices[3] == ARM::ssub_3) {
282        if (Size >= 256)
283          NewSubIdx = ARM::qsub_0;
284        return true;
285      }
286    }
287  } else if (NumRegs == 2) {
288    if (SubIndices[0] == ARM::qsub_0) {
289      // 2 Q registers -> 1 QQ register.
290      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
291        if (Size == 512)
292          NewSubIdx = ARM::qqsub_0;
293        return true;
294      }
295    } else if (SubIndices[0] == ARM::qsub_2) {
296      // 2 Q registers -> 1 QQ register (2nd).
297      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
298        NewSubIdx = ARM::qqsub_1;
299        return true;
300      }
301    } else if (SubIndices[0] == ARM::dsub_0) {
302      // 2 D registers -> 1 Q register.
303      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
304        if (Size >= 256)
305          NewSubIdx = ARM::qsub_0;
306        return true;
307      }
308    } else if (SubIndices[0] == ARM::dsub_2) {
309      // 2 D registers -> 1 Q register (2nd).
310      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
311        NewSubIdx = ARM::qsub_1;
312        return true;
313      }
314    } else if (SubIndices[0] == ARM::dsub_4) {
315      // 2 D registers -> 1 Q register (3rd).
316      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
317        NewSubIdx = ARM::qsub_2;
318        return true;
319      }
320    } else if (SubIndices[0] == ARM::dsub_6) {
321      // 2 D registers -> 1 Q register (3rd).
322      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
323        NewSubIdx = ARM::qsub_3;
324        return true;
325      }
326    } else if (SubIndices[0] == ARM::ssub_0) {
327      // 2 S registers -> 1 D register.
328      if (SubIndices[1] == ARM::ssub_1) {
329        if (Size >= 128)
330          NewSubIdx = ARM::dsub_0;
331        return true;
332      }
333    } else if (SubIndices[0] == ARM::ssub_2) {
334      // 2 S registers -> 1 D register (2nd).
335      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
336        NewSubIdx = ARM::dsub_1;
337        return true;
338      }
339    }
340  }
341  return false;
342}
343
344
345const TargetRegisterClass *
346ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
347  return ARM::GPRRegisterClass;
348}
349
350/// getAllocationOrder - Returns the register allocation order for a specified
351/// register class in the form of a pair of TargetRegisterClass iterators.
352std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
353ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
354                                        unsigned HintType, unsigned HintReg,
355                                        const MachineFunction &MF) const {
356  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
357  // Alternative register allocation orders when favoring even / odd registers
358  // of register pairs.
359
360  // No FP, R9 is available.
361  static const unsigned GPREven1[] = {
362    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
363    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
364    ARM::R9, ARM::R11
365  };
366  static const unsigned GPROdd1[] = {
367    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
368    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
369    ARM::R8, ARM::R10
370  };
371
372  // FP is R7, R9 is available.
373  static const unsigned GPREven2[] = {
374    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
375    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
376    ARM::R9, ARM::R11
377  };
378  static const unsigned GPROdd2[] = {
379    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
380    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
381    ARM::R8, ARM::R10
382  };
383
384  // FP is R11, R9 is available.
385  static const unsigned GPREven3[] = {
386    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
387    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
388    ARM::R9
389  };
390  static const unsigned GPROdd3[] = {
391    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
392    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
393    ARM::R8
394  };
395
396  // No FP, R9 is not available.
397  static const unsigned GPREven4[] = {
398    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
399    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
400    ARM::R11
401  };
402  static const unsigned GPROdd4[] = {
403    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
404    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
405    ARM::R10
406  };
407
408  // FP is R7, R9 is not available.
409  static const unsigned GPREven5[] = {
410    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
411    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
412    ARM::R11
413  };
414  static const unsigned GPROdd5[] = {
415    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
416    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
417    ARM::R10
418  };
419
420  // FP is R11, R9 is not available.
421  static const unsigned GPREven6[] = {
422    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
423    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
424  };
425  static const unsigned GPROdd6[] = {
426    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
427    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
428  };
429
430
431  if (HintType == ARMRI::RegPairEven) {
432    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
433      // It's no longer possible to fulfill this hint. Return the default
434      // allocation order.
435      return std::make_pair(RC->allocation_order_begin(MF),
436                            RC->allocation_order_end(MF));
437
438    if (!TFI->hasFP(MF)) {
439      if (!STI.isR9Reserved())
440        return std::make_pair(GPREven1,
441                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
442      else
443        return std::make_pair(GPREven4,
444                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
445    } else if (FramePtr == ARM::R7) {
446      if (!STI.isR9Reserved())
447        return std::make_pair(GPREven2,
448                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
449      else
450        return std::make_pair(GPREven5,
451                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
452    } else { // FramePtr == ARM::R11
453      if (!STI.isR9Reserved())
454        return std::make_pair(GPREven3,
455                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
456      else
457        return std::make_pair(GPREven6,
458                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
459    }
460  } else if (HintType == ARMRI::RegPairOdd) {
461    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
462      // It's no longer possible to fulfill this hint. Return the default
463      // allocation order.
464      return std::make_pair(RC->allocation_order_begin(MF),
465                            RC->allocation_order_end(MF));
466
467    if (!TFI->hasFP(MF)) {
468      if (!STI.isR9Reserved())
469        return std::make_pair(GPROdd1,
470                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
471      else
472        return std::make_pair(GPROdd4,
473                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
474    } else if (FramePtr == ARM::R7) {
475      if (!STI.isR9Reserved())
476        return std::make_pair(GPROdd2,
477                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
478      else
479        return std::make_pair(GPROdd5,
480                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
481    } else { // FramePtr == ARM::R11
482      if (!STI.isR9Reserved())
483        return std::make_pair(GPROdd3,
484                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
485      else
486        return std::make_pair(GPROdd6,
487                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
488    }
489  }
490  return std::make_pair(RC->allocation_order_begin(MF),
491                        RC->allocation_order_end(MF));
492}
493
494/// ResolveRegAllocHint - Resolves the specified register allocation hint
495/// to a physical register. Returns the physical register if it is successful.
496unsigned
497ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
498                                         const MachineFunction &MF) const {
499  if (Reg == 0 || !isPhysicalRegister(Reg))
500    return 0;
501  if (Type == 0)
502    return Reg;
503  else if (Type == (unsigned)ARMRI::RegPairOdd)
504    // Odd register.
505    return getRegisterPairOdd(Reg, MF);
506  else if (Type == (unsigned)ARMRI::RegPairEven)
507    // Even register.
508    return getRegisterPairEven(Reg, MF);
509  return 0;
510}
511
512void
513ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
514                                        MachineFunction &MF) const {
515  MachineRegisterInfo *MRI = &MF.getRegInfo();
516  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
517  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
518       Hint.first == (unsigned)ARMRI::RegPairEven) &&
519      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
520    // If 'Reg' is one of the even / odd register pair and it's now changed
521    // (e.g. coalesced) into a different register. The other register of the
522    // pair allocation hint must be updated to reflect the relationship
523    // change.
524    unsigned OtherReg = Hint.second;
525    Hint = MRI->getRegAllocationHint(OtherReg);
526    if (Hint.second == Reg)
527      // Make sure the pair has not already divorced.
528      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
529  }
530}
531
532bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
533  const MachineFrameInfo *MFI = MF.getFrameInfo();
534  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
535
536  if (!EnableBasePointer)
537    return false;
538
539  if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
540    return true;
541
542  // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
543  // negative range for ldr/str (255), and thumb1 is positive offsets only.
544  // It's going to be better to use the SP or Base Pointer instead. When there
545  // are variable sized objects, we can't reference off of the SP, so we
546  // reserve a Base Pointer.
547  if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
548    // Conservatively estimate whether the negative offset from the frame
549    // pointer will be sufficient to reach. If a function has a smallish
550    // frame, it's less likely to have lots of spills and callee saved
551    // space, so it's all more likely to be within range of the frame pointer.
552    // If it's wrong, the scavenger will still enable access to work, it just
553    // won't be optimal.
554    if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
555      return false;
556    return true;
557  }
558
559  return false;
560}
561
562bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
563  const MachineFrameInfo *MFI = MF.getFrameInfo();
564  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
565  // We can't realign the stack if:
566  // 1. Dynamic stack realignment is explicitly disabled,
567  // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
568  // 3. There are VLAs in the function and the base pointer is disabled.
569  return (RealignStack && !AFI->isThumb1OnlyFunction() &&
570          (!MFI->hasVarSizedObjects() || EnableBasePointer));
571}
572
573bool ARMBaseRegisterInfo::
574needsStackRealignment(const MachineFunction &MF) const {
575  const MachineFrameInfo *MFI = MF.getFrameInfo();
576  const Function *F = MF.getFunction();
577  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
578  bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
579                               F->hasFnAttr(Attribute::StackAlignment));
580
581  return requiresRealignment && canRealignStack(MF);
582}
583
584bool ARMBaseRegisterInfo::
585cannotEliminateFrame(const MachineFunction &MF) const {
586  const MachineFrameInfo *MFI = MF.getFrameInfo();
587  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
588    return true;
589  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
590    || needsStackRealignment(MF);
591}
592
593/// estimateStackSize - Estimate and return the size of the frame.
594static unsigned estimateStackSize(MachineFunction &MF) {
595  const MachineFrameInfo *FFI = MF.getFrameInfo();
596  int Offset = 0;
597  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
598    int FixedOff = -FFI->getObjectOffset(i);
599    if (FixedOff > Offset) Offset = FixedOff;
600  }
601  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
602    if (FFI->isDeadObjectIndex(i))
603      continue;
604    Offset += FFI->getObjectSize(i);
605    unsigned Align = FFI->getObjectAlignment(i);
606    // Adjust to alignment boundary
607    Offset = (Offset+Align-1)/Align*Align;
608  }
609  return (unsigned)Offset;
610}
611
612/// estimateRSStackSizeLimit - Look at each instruction that references stack
613/// frames and return the stack size limit beyond which some of these
614/// instructions will require a scratch register during their expansion later.
615unsigned
616ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
617  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
618  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
619  unsigned Limit = (1 << 12) - 1;
620  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
621    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
622         I != E; ++I) {
623      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
624        if (!I->getOperand(i).isFI()) continue;
625
626        // When using ADDri to get the address of a stack object, 255 is the
627        // largest offset guaranteed to fit in the immediate offset.
628        if (I->getOpcode() == ARM::ADDri) {
629          Limit = std::min(Limit, (1U << 8) - 1);
630          break;
631        }
632
633        // Otherwise check the addressing mode.
634        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
635        case ARMII::AddrMode3:
636        case ARMII::AddrModeT2_i8:
637          Limit = std::min(Limit, (1U << 8) - 1);
638          break;
639        case ARMII::AddrMode5:
640        case ARMII::AddrModeT2_i8s4:
641          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
642          break;
643        case ARMII::AddrModeT2_i12:
644          // i12 supports only positive offset so these will be converted to
645          // i8 opcodes. See llvm::rewriteT2FrameIndex.
646          if (TFI->hasFP(MF) && AFI->hasStackFrame())
647            Limit = std::min(Limit, (1U << 8) - 1);
648          break;
649        case ARMII::AddrMode4:
650        case ARMII::AddrMode6:
651          // Addressing modes 4 & 6 (load/store) instructions can't encode an
652          // immediate offset for stack references.
653          return 0;
654        default:
655          break;
656        }
657        break; // At most one FI per instruction
658      }
659    }
660  }
661
662  return Limit;
663}
664
665static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
666                                       const ARMBaseInstrInfo &TII) {
667  unsigned FnSize = 0;
668  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
669       MBBI != E; ++MBBI) {
670    const MachineBasicBlock &MBB = *MBBI;
671    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
672         I != E; ++I)
673      FnSize += TII.GetInstSizeInBytes(I);
674  }
675  return FnSize;
676}
677
678void
679ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
680                                                       RegScavenger *RS) const {
681  // This tells PEI to spill the FP as if it is any other callee-save register
682  // to take advantage the eliminateFrameIndex machinery. This also ensures it
683  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
684  // to combine multiple loads / stores.
685  bool CanEliminateFrame = true;
686  bool CS1Spilled = false;
687  bool LRSpilled = false;
688  unsigned NumGPRSpills = 0;
689  SmallVector<unsigned, 4> UnspilledCS1GPRs;
690  SmallVector<unsigned, 4> UnspilledCS2GPRs;
691  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
692  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
693  MachineFrameInfo *MFI = MF.getFrameInfo();
694
695  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
696  // scratch register.
697  // FIXME: It will be better just to find spare register here.
698  if (needsStackRealignment(MF) &&
699      AFI->isThumb2Function())
700    MF.getRegInfo().setPhysRegUsed(ARM::R4);
701
702  // Spill LR if Thumb1 function uses variable length argument lists.
703  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
704    MF.getRegInfo().setPhysRegUsed(ARM::LR);
705
706  // Spill the BasePtr if it's used.
707  if (hasBasePointer(MF))
708    MF.getRegInfo().setPhysRegUsed(BasePtr);
709
710  // Don't spill FP if the frame can be eliminated. This is determined
711  // by scanning the callee-save registers to see if any is used.
712  const unsigned *CSRegs = getCalleeSavedRegs();
713  for (unsigned i = 0; CSRegs[i]; ++i) {
714    unsigned Reg = CSRegs[i];
715    bool Spilled = false;
716    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
717      AFI->setCSRegisterIsSpilled(Reg);
718      Spilled = true;
719      CanEliminateFrame = false;
720    } else {
721      // Check alias registers too.
722      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
723        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
724          Spilled = true;
725          CanEliminateFrame = false;
726        }
727      }
728    }
729
730    if (!ARM::GPRRegisterClass->contains(Reg))
731      continue;
732
733    if (Spilled) {
734      NumGPRSpills++;
735
736      if (!STI.isTargetDarwin()) {
737        if (Reg == ARM::LR)
738          LRSpilled = true;
739        CS1Spilled = true;
740        continue;
741      }
742
743      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
744      switch (Reg) {
745      case ARM::LR:
746        LRSpilled = true;
747        // Fallthrough
748      case ARM::R4:
749      case ARM::R5:
750      case ARM::R6:
751      case ARM::R7:
752        CS1Spilled = true;
753        break;
754      default:
755        break;
756      }
757    } else {
758      if (!STI.isTargetDarwin()) {
759        UnspilledCS1GPRs.push_back(Reg);
760        continue;
761      }
762
763      switch (Reg) {
764      case ARM::R4:
765      case ARM::R5:
766      case ARM::R6:
767      case ARM::R7:
768      case ARM::LR:
769        UnspilledCS1GPRs.push_back(Reg);
770        break;
771      default:
772        UnspilledCS2GPRs.push_back(Reg);
773        break;
774      }
775    }
776  }
777
778  bool ForceLRSpill = false;
779  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
780    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
781    // Force LR to be spilled if the Thumb function size is > 2048. This enables
782    // use of BL to implement far jump. If it turns out that it's not needed
783    // then the branch fix up path will undo it.
784    if (FnSize >= (1 << 11)) {
785      CanEliminateFrame = false;
786      ForceLRSpill = true;
787    }
788  }
789
790  // If any of the stack slot references may be out of range of an immediate
791  // offset, make sure a register (or a spill slot) is available for the
792  // register scavenger. Note that if we're indexing off the frame pointer, the
793  // effective stack size is 4 bytes larger since the FP points to the stack
794  // slot of the previous FP. Also, if we have variable sized objects in the
795  // function, stack slot references will often be negative, and some of
796  // our instructions are positive-offset only, so conservatively consider
797  // that case to want a spill slot (or register) as well. Similarly, if
798  // the function adjusts the stack pointer during execution and the
799  // adjustments aren't already part of our stack size estimate, our offset
800  // calculations may be off, so be conservative.
801  // FIXME: We could add logic to be more precise about negative offsets
802  //        and which instructions will need a scratch register for them. Is it
803  //        worth the effort and added fragility?
804  bool BigStack =
805    (RS &&
806     (estimateStackSize(MF) + ((TFI->hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
807      estimateRSStackSizeLimit(MF)))
808    || MFI->hasVarSizedObjects()
809    || (MFI->adjustsStack() && !TFI->canSimplifyCallFramePseudos(MF));
810
811  bool ExtraCSSpill = false;
812  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
813    AFI->setHasStackFrame(true);
814
815    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
816    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
817    if (!LRSpilled && CS1Spilled) {
818      MF.getRegInfo().setPhysRegUsed(ARM::LR);
819      AFI->setCSRegisterIsSpilled(ARM::LR);
820      NumGPRSpills++;
821      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
822                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
823      ForceLRSpill = false;
824      ExtraCSSpill = true;
825    }
826
827    if (TFI->hasFP(MF)) {
828      MF.getRegInfo().setPhysRegUsed(FramePtr);
829      NumGPRSpills++;
830    }
831
832    // If stack and double are 8-byte aligned and we are spilling an odd number
833    // of GPRs, spill one extra callee save GPR so we won't have to pad between
834    // the integer and double callee save areas.
835    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
836    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
837      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
838        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
839          unsigned Reg = UnspilledCS1GPRs[i];
840          // Don't spill high register if the function is thumb1
841          if (!AFI->isThumb1OnlyFunction() ||
842              isARMLowRegister(Reg) || Reg == ARM::LR) {
843            MF.getRegInfo().setPhysRegUsed(Reg);
844            AFI->setCSRegisterIsSpilled(Reg);
845            if (!isReservedReg(MF, Reg))
846              ExtraCSSpill = true;
847            break;
848          }
849        }
850      } else if (!UnspilledCS2GPRs.empty() &&
851                 !AFI->isThumb1OnlyFunction()) {
852        unsigned Reg = UnspilledCS2GPRs.front();
853        MF.getRegInfo().setPhysRegUsed(Reg);
854        AFI->setCSRegisterIsSpilled(Reg);
855        if (!isReservedReg(MF, Reg))
856          ExtraCSSpill = true;
857      }
858    }
859
860    // Estimate if we might need to scavenge a register at some point in order
861    // to materialize a stack offset. If so, either spill one additional
862    // callee-saved register or reserve a special spill slot to facilitate
863    // register scavenging. Thumb1 needs a spill slot for stack pointer
864    // adjustments also, even when the frame itself is small.
865    if (BigStack && !ExtraCSSpill) {
866      // If any non-reserved CS register isn't spilled, just spill one or two
867      // extra. That should take care of it!
868      unsigned NumExtras = TargetAlign / 4;
869      SmallVector<unsigned, 2> Extras;
870      while (NumExtras && !UnspilledCS1GPRs.empty()) {
871        unsigned Reg = UnspilledCS1GPRs.back();
872        UnspilledCS1GPRs.pop_back();
873        if (!isReservedReg(MF, Reg) &&
874            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
875             Reg == ARM::LR)) {
876          Extras.push_back(Reg);
877          NumExtras--;
878        }
879      }
880      // For non-Thumb1 functions, also check for hi-reg CS registers
881      if (!AFI->isThumb1OnlyFunction()) {
882        while (NumExtras && !UnspilledCS2GPRs.empty()) {
883          unsigned Reg = UnspilledCS2GPRs.back();
884          UnspilledCS2GPRs.pop_back();
885          if (!isReservedReg(MF, Reg)) {
886            Extras.push_back(Reg);
887            NumExtras--;
888          }
889        }
890      }
891      if (Extras.size() && NumExtras == 0) {
892        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
893          MF.getRegInfo().setPhysRegUsed(Extras[i]);
894          AFI->setCSRegisterIsSpilled(Extras[i]);
895        }
896      } else if (!AFI->isThumb1OnlyFunction()) {
897        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
898        // closest to SP or frame pointer.
899        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
900        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
901                                                           RC->getAlignment(),
902                                                           false));
903      }
904    }
905  }
906
907  if (ForceLRSpill) {
908    MF.getRegInfo().setPhysRegUsed(ARM::LR);
909    AFI->setCSRegisterIsSpilled(ARM::LR);
910    AFI->setLRIsSpilledForFarJump(true);
911  }
912}
913
914unsigned ARMBaseRegisterInfo::getRARegister() const {
915  return ARM::LR;
916}
917
918unsigned
919ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
920  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
921
922  if (TFI->hasFP(MF))
923    return FramePtr;
924  return ARM::SP;
925}
926
927// Provide a base+offset reference to an FI slot for debug info. It's the
928// same as what we use for resolving the code-gen references for now.
929// FIXME: This can go wrong when references are SP-relative and simple call
930//        frames aren't used.
931int
932ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
933                                            unsigned &FrameReg) const {
934  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
935}
936
937int
938ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
939                                                int FI,
940                                                unsigned &FrameReg,
941                                                int SPAdj) const {
942  const MachineFrameInfo *MFI = MF.getFrameInfo();
943  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
944  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
945  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
946  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
947  bool isFixed = MFI->isFixedObjectIndex(FI);
948
949  FrameReg = ARM::SP;
950  Offset += SPAdj;
951  if (AFI->isGPRCalleeSavedArea1Frame(FI))
952    return Offset - AFI->getGPRCalleeSavedArea1Offset();
953  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
954    return Offset - AFI->getGPRCalleeSavedArea2Offset();
955  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
956    return Offset - AFI->getDPRCalleeSavedAreaOffset();
957
958  // When dynamically realigning the stack, use the frame pointer for
959  // parameters, and the stack/base pointer for locals.
960  if (needsStackRealignment(MF)) {
961    assert (TFI->hasFP(MF) && "dynamic stack realignment without a FP!");
962    if (isFixed) {
963      FrameReg = getFrameRegister(MF);
964      Offset = FPOffset;
965    } else if (MFI->hasVarSizedObjects()) {
966      assert(hasBasePointer(MF) &&
967             "VLAs and dynamic stack alignment, but missing base pointer!");
968      FrameReg = BasePtr;
969    }
970    return Offset;
971  }
972
973  // If there is a frame pointer, use it when we can.
974  if (TFI->hasFP(MF) && AFI->hasStackFrame()) {
975    // Use frame pointer to reference fixed objects. Use it for locals if
976    // there are VLAs (and thus the SP isn't reliable as a base).
977    if (isFixed || (MFI->hasVarSizedObjects() && !hasBasePointer(MF))) {
978      FrameReg = getFrameRegister(MF);
979      return FPOffset;
980    } else if (MFI->hasVarSizedObjects()) {
981      assert(hasBasePointer(MF) && "missing base pointer!");
982      // Try to use the frame pointer if we can, else use the base pointer
983      // since it's available. This is handy for the emergency spill slot, in
984      // particular.
985      if (AFI->isThumb2Function()) {
986        if (FPOffset >= -255 && FPOffset < 0) {
987          FrameReg = getFrameRegister(MF);
988          return FPOffset;
989        }
990      } else
991        FrameReg = BasePtr;
992    } else if (AFI->isThumb2Function()) {
993      // In Thumb2 mode, the negative offset is very limited. Try to avoid
994      // out of range references.
995      if (FPOffset >= -255 && FPOffset < 0) {
996        FrameReg = getFrameRegister(MF);
997        return FPOffset;
998      }
999    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1000      // Otherwise, use SP or FP, whichever is closer to the stack slot.
1001      FrameReg = getFrameRegister(MF);
1002      return FPOffset;
1003    }
1004  }
1005  // Use the base pointer if we have one.
1006  if (hasBasePointer(MF))
1007    FrameReg = BasePtr;
1008  return Offset;
1009}
1010
1011int
1012ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1013                                         int FI) const {
1014  unsigned FrameReg;
1015  return getFrameIndexReference(MF, FI, FrameReg);
1016}
1017
1018unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1019  llvm_unreachable("What is the exception register");
1020  return 0;
1021}
1022
1023unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1024  llvm_unreachable("What is the exception handler register");
1025  return 0;
1026}
1027
1028int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1029  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1030}
1031
1032unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1033                                              const MachineFunction &MF) const {
1034  switch (Reg) {
1035  default: break;
1036  // Return 0 if either register of the pair is a special register.
1037  // So no R12, etc.
1038  case ARM::R1:
1039    return ARM::R0;
1040  case ARM::R3:
1041    return ARM::R2;
1042  case ARM::R5:
1043    return ARM::R4;
1044  case ARM::R7:
1045    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1046      ? 0 : ARM::R6;
1047  case ARM::R9:
1048    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1049  case ARM::R11:
1050    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1051
1052  case ARM::S1:
1053    return ARM::S0;
1054  case ARM::S3:
1055    return ARM::S2;
1056  case ARM::S5:
1057    return ARM::S4;
1058  case ARM::S7:
1059    return ARM::S6;
1060  case ARM::S9:
1061    return ARM::S8;
1062  case ARM::S11:
1063    return ARM::S10;
1064  case ARM::S13:
1065    return ARM::S12;
1066  case ARM::S15:
1067    return ARM::S14;
1068  case ARM::S17:
1069    return ARM::S16;
1070  case ARM::S19:
1071    return ARM::S18;
1072  case ARM::S21:
1073    return ARM::S20;
1074  case ARM::S23:
1075    return ARM::S22;
1076  case ARM::S25:
1077    return ARM::S24;
1078  case ARM::S27:
1079    return ARM::S26;
1080  case ARM::S29:
1081    return ARM::S28;
1082  case ARM::S31:
1083    return ARM::S30;
1084
1085  case ARM::D1:
1086    return ARM::D0;
1087  case ARM::D3:
1088    return ARM::D2;
1089  case ARM::D5:
1090    return ARM::D4;
1091  case ARM::D7:
1092    return ARM::D6;
1093  case ARM::D9:
1094    return ARM::D8;
1095  case ARM::D11:
1096    return ARM::D10;
1097  case ARM::D13:
1098    return ARM::D12;
1099  case ARM::D15:
1100    return ARM::D14;
1101  case ARM::D17:
1102    return ARM::D16;
1103  case ARM::D19:
1104    return ARM::D18;
1105  case ARM::D21:
1106    return ARM::D20;
1107  case ARM::D23:
1108    return ARM::D22;
1109  case ARM::D25:
1110    return ARM::D24;
1111  case ARM::D27:
1112    return ARM::D26;
1113  case ARM::D29:
1114    return ARM::D28;
1115  case ARM::D31:
1116    return ARM::D30;
1117  }
1118
1119  return 0;
1120}
1121
1122unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1123                                             const MachineFunction &MF) const {
1124  switch (Reg) {
1125  default: break;
1126  // Return 0 if either register of the pair is a special register.
1127  // So no R12, etc.
1128  case ARM::R0:
1129    return ARM::R1;
1130  case ARM::R2:
1131    return ARM::R3;
1132  case ARM::R4:
1133    return ARM::R5;
1134  case ARM::R6:
1135    return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
1136      ? 0 : ARM::R7;
1137  case ARM::R8:
1138    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1139  case ARM::R10:
1140    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1141
1142  case ARM::S0:
1143    return ARM::S1;
1144  case ARM::S2:
1145    return ARM::S3;
1146  case ARM::S4:
1147    return ARM::S5;
1148  case ARM::S6:
1149    return ARM::S7;
1150  case ARM::S8:
1151    return ARM::S9;
1152  case ARM::S10:
1153    return ARM::S11;
1154  case ARM::S12:
1155    return ARM::S13;
1156  case ARM::S14:
1157    return ARM::S15;
1158  case ARM::S16:
1159    return ARM::S17;
1160  case ARM::S18:
1161    return ARM::S19;
1162  case ARM::S20:
1163    return ARM::S21;
1164  case ARM::S22:
1165    return ARM::S23;
1166  case ARM::S24:
1167    return ARM::S25;
1168  case ARM::S26:
1169    return ARM::S27;
1170  case ARM::S28:
1171    return ARM::S29;
1172  case ARM::S30:
1173    return ARM::S31;
1174
1175  case ARM::D0:
1176    return ARM::D1;
1177  case ARM::D2:
1178    return ARM::D3;
1179  case ARM::D4:
1180    return ARM::D5;
1181  case ARM::D6:
1182    return ARM::D7;
1183  case ARM::D8:
1184    return ARM::D9;
1185  case ARM::D10:
1186    return ARM::D11;
1187  case ARM::D12:
1188    return ARM::D13;
1189  case ARM::D14:
1190    return ARM::D15;
1191  case ARM::D16:
1192    return ARM::D17;
1193  case ARM::D18:
1194    return ARM::D19;
1195  case ARM::D20:
1196    return ARM::D21;
1197  case ARM::D22:
1198    return ARM::D23;
1199  case ARM::D24:
1200    return ARM::D25;
1201  case ARM::D26:
1202    return ARM::D27;
1203  case ARM::D28:
1204    return ARM::D29;
1205  case ARM::D30:
1206    return ARM::D31;
1207  }
1208
1209  return 0;
1210}
1211
1212/// emitLoadConstPool - Emits a load from constpool to materialize the
1213/// specified immediate.
1214void ARMBaseRegisterInfo::
1215emitLoadConstPool(MachineBasicBlock &MBB,
1216                  MachineBasicBlock::iterator &MBBI,
1217                  DebugLoc dl,
1218                  unsigned DestReg, unsigned SubIdx, int Val,
1219                  ARMCC::CondCodes Pred,
1220                  unsigned PredReg) const {
1221  MachineFunction &MF = *MBB.getParent();
1222  MachineConstantPool *ConstantPool = MF.getConstantPool();
1223  const Constant *C =
1224        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1225  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1226
1227  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1228    .addReg(DestReg, getDefRegState(true), SubIdx)
1229    .addConstantPoolIndex(Idx)
1230    .addImm(0).addImm(Pred).addReg(PredReg);
1231}
1232
1233bool ARMBaseRegisterInfo::
1234requiresRegisterScavenging(const MachineFunction &MF) const {
1235  return true;
1236}
1237
1238bool ARMBaseRegisterInfo::
1239requiresFrameIndexScavenging(const MachineFunction &MF) const {
1240  return true;
1241}
1242
1243bool ARMBaseRegisterInfo::
1244requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1245  return EnableLocalStackAlloc;
1246}
1247
1248static void
1249emitSPUpdate(bool isARM,
1250             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1251             DebugLoc dl, const ARMBaseInstrInfo &TII,
1252             int NumBytes,
1253             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1254  if (isARM)
1255    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1256                            Pred, PredReg, TII);
1257  else
1258    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1259                           Pred, PredReg, TII);
1260}
1261
1262
1263void ARMBaseRegisterInfo::
1264eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1265                              MachineBasicBlock::iterator I) const {
1266  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1267  if (!TFI->hasReservedCallFrame(MF)) {
1268    // If we have alloca, convert as follows:
1269    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1270    // ADJCALLSTACKUP   -> add, sp, sp, amount
1271    MachineInstr *Old = I;
1272    DebugLoc dl = Old->getDebugLoc();
1273    unsigned Amount = Old->getOperand(0).getImm();
1274    if (Amount != 0) {
1275      // We need to keep the stack aligned properly.  To do this, we round the
1276      // amount of space needed for the outgoing arguments up to the next
1277      // alignment boundary.
1278      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1279      Amount = (Amount+Align-1)/Align*Align;
1280
1281      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1282      assert(!AFI->isThumb1OnlyFunction() &&
1283             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1284      bool isARM = !AFI->isThumbFunction();
1285
1286      // Replace the pseudo instruction with a new instruction...
1287      unsigned Opc = Old->getOpcode();
1288      int PIdx = Old->findFirstPredOperandIdx();
1289      ARMCC::CondCodes Pred = (PIdx == -1)
1290        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1291      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1292        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1293        unsigned PredReg = Old->getOperand(2).getReg();
1294        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1295      } else {
1296        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1297        unsigned PredReg = Old->getOperand(3).getReg();
1298        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1299        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1300      }
1301    }
1302  }
1303  MBB.erase(I);
1304}
1305
1306int64_t ARMBaseRegisterInfo::
1307getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1308  const TargetInstrDesc &Desc = MI->getDesc();
1309  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1310  int64_t InstrOffs = 0;;
1311  int Scale = 1;
1312  unsigned ImmIdx = 0;
1313  switch (AddrMode) {
1314  case ARMII::AddrModeT2_i8:
1315  case ARMII::AddrModeT2_i12:
1316  case ARMII::AddrMode_i12:
1317    InstrOffs = MI->getOperand(Idx+1).getImm();
1318    Scale = 1;
1319    break;
1320  case ARMII::AddrMode5: {
1321    // VFP address mode.
1322    const MachineOperand &OffOp = MI->getOperand(Idx+1);
1323    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1324    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1325      InstrOffs = -InstrOffs;
1326    Scale = 4;
1327    break;
1328  }
1329  case ARMII::AddrMode2: {
1330    ImmIdx = Idx+2;
1331    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1332    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1333      InstrOffs = -InstrOffs;
1334    break;
1335  }
1336  case ARMII::AddrMode3: {
1337    ImmIdx = Idx+2;
1338    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1339    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1340      InstrOffs = -InstrOffs;
1341    break;
1342  }
1343  case ARMII::AddrModeT1_s: {
1344    ImmIdx = Idx+1;
1345    InstrOffs = MI->getOperand(ImmIdx).getImm();
1346    Scale = 4;
1347    break;
1348  }
1349  default:
1350    llvm_unreachable("Unsupported addressing mode!");
1351    break;
1352  }
1353
1354  return InstrOffs * Scale;
1355}
1356
1357/// needsFrameBaseReg - Returns true if the instruction's frame index
1358/// reference would be better served by a base register other than FP
1359/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1360/// references it should create new base registers for.
1361bool ARMBaseRegisterInfo::
1362needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1363  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1364    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1365  }
1366
1367  // It's the load/store FI references that cause issues, as it can be difficult
1368  // to materialize the offset if it won't fit in the literal field. Estimate
1369  // based on the size of the local frame and some conservative assumptions
1370  // about the rest of the stack frame (note, this is pre-regalloc, so
1371  // we don't know everything for certain yet) whether this offset is likely
1372  // to be out of range of the immediate. Return true if so.
1373
1374  // We only generate virtual base registers for loads and stores, so
1375  // return false for everything else.
1376  unsigned Opc = MI->getOpcode();
1377  switch (Opc) {
1378  case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
1379  case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
1380  case ARM::t2LDRi12: case ARM::t2LDRi8:
1381  case ARM::t2STRi12: case ARM::t2STRi8:
1382  case ARM::VLDRS: case ARM::VLDRD:
1383  case ARM::VSTRS: case ARM::VSTRD:
1384  case ARM::tSTRspi: case ARM::tLDRspi:
1385    if (ForceAllBaseRegAlloc)
1386      return true;
1387    break;
1388  default:
1389    return false;
1390  }
1391
1392  // Without a virtual base register, if the function has variable sized
1393  // objects, all fixed-size local references will be via the frame pointer,
1394  // Approximate the offset and see if it's legal for the instruction.
1395  // Note that the incoming offset is based on the SP value at function entry,
1396  // so it'll be negative.
1397  MachineFunction &MF = *MI->getParent()->getParent();
1398  const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
1399  MachineFrameInfo *MFI = MF.getFrameInfo();
1400  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1401
1402  // Estimate an offset from the frame pointer.
1403  // Conservatively assume all callee-saved registers get pushed. R4-R6
1404  // will be earlier than the FP, so we ignore those.
1405  // R7, LR
1406  int64_t FPOffset = Offset - 8;
1407  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1408  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1409    FPOffset -= 80;
1410  // Estimate an offset from the stack pointer.
1411  // The incoming offset is relating to the SP at the start of the function,
1412  // but when we access the local it'll be relative to the SP after local
1413  // allocation, so adjust our SP-relative offset by that allocation size.
1414  Offset = -Offset;
1415  Offset += MFI->getLocalFrameSize();
1416  // Assume that we'll have at least some spill slots allocated.
1417  // FIXME: This is a total SWAG number. We should run some statistics
1418  //        and pick a real one.
1419  Offset += 128; // 128 bytes of spill slots
1420
1421  // If there is a frame pointer, try using it.
1422  // The FP is only available if there is no dynamic realignment. We
1423  // don't know for sure yet whether we'll need that, so we guess based
1424  // on whether there are any local variables that would trigger it.
1425  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1426  if (TFI->hasFP(MF) &&
1427      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1428    if (isFrameOffsetLegal(MI, FPOffset))
1429      return false;
1430  }
1431  // If we can reference via the stack pointer, try that.
1432  // FIXME: This (and the code that resolves the references) can be improved
1433  //        to only disallow SP relative references in the live range of
1434  //        the VLA(s). In practice, it's unclear how much difference that
1435  //        would make, but it may be worth doing.
1436  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1437    return false;
1438
1439  // The offset likely isn't legal, we want to allocate a virtual base register.
1440  return true;
1441}
1442
1443/// materializeFrameBaseRegister - Insert defining instruction(s) for
1444/// BaseReg to be a pointer to FrameIdx before insertion point I.
1445void ARMBaseRegisterInfo::
1446materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1447                             int FrameIdx, int64_t Offset) const {
1448  ARMFunctionInfo *AFI =
1449    I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1450  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1451    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1452
1453  MachineInstrBuilder MIB =
1454    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1455    .addFrameIndex(FrameIdx).addImm(Offset);
1456  if (!AFI->isThumb1OnlyFunction())
1457    AddDefaultCC(AddDefaultPred(MIB));
1458}
1459
1460void
1461ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1462                                       unsigned BaseReg, int64_t Offset) const {
1463  MachineInstr &MI = *I;
1464  MachineBasicBlock &MBB = *MI.getParent();
1465  MachineFunction &MF = *MBB.getParent();
1466  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1467  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1468  unsigned i = 0;
1469
1470  assert(!AFI->isThumb1OnlyFunction() &&
1471         "This resolveFrameIndex does not support Thumb1!");
1472
1473  while (!MI.getOperand(i).isFI()) {
1474    ++i;
1475    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1476  }
1477  bool Done = false;
1478  if (!AFI->isThumbFunction())
1479    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1480  else {
1481    assert(AFI->isThumb2Function());
1482    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1483  }
1484  assert (Done && "Unable to resolve frame index!");
1485}
1486
1487bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1488                                             int64_t Offset) const {
1489  const TargetInstrDesc &Desc = MI->getDesc();
1490  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1491  unsigned i = 0;
1492
1493  while (!MI->getOperand(i).isFI()) {
1494    ++i;
1495    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1496  }
1497
1498  // AddrMode4 and AddrMode6 cannot handle any offset.
1499  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1500    return Offset == 0;
1501
1502  unsigned NumBits = 0;
1503  unsigned Scale = 1;
1504  bool isSigned = true;
1505  switch (AddrMode) {
1506  case ARMII::AddrModeT2_i8:
1507  case ARMII::AddrModeT2_i12:
1508    // i8 supports only negative, and i12 supports only positive, so
1509    // based on Offset sign, consider the appropriate instruction
1510    Scale = 1;
1511    if (Offset < 0) {
1512      NumBits = 8;
1513      Offset = -Offset;
1514    } else {
1515      NumBits = 12;
1516    }
1517    break;
1518  case ARMII::AddrMode5:
1519    // VFP address mode.
1520    NumBits = 8;
1521    Scale = 4;
1522    break;
1523  case ARMII::AddrMode_i12:
1524  case ARMII::AddrMode2:
1525    NumBits = 12;
1526    break;
1527  case ARMII::AddrMode3:
1528    NumBits = 8;
1529    break;
1530  case ARMII::AddrModeT1_s:
1531    NumBits = 5;
1532    Scale = 4;
1533    isSigned = false;
1534    break;
1535  default:
1536    llvm_unreachable("Unsupported addressing mode!");
1537    break;
1538  }
1539
1540  Offset += getFrameIndexInstrOffset(MI, i);
1541  // Make sure the offset is encodable for instructions that scale the
1542  // immediate.
1543  if ((Offset & (Scale-1)) != 0)
1544    return false;
1545
1546  if (isSigned && Offset < 0)
1547    Offset = -Offset;
1548
1549  unsigned Mask = (1 << NumBits) - 1;
1550  if ((unsigned)Offset <= Mask * Scale)
1551    return true;
1552
1553  return false;
1554}
1555
1556void
1557ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1558                                         int SPAdj, RegScavenger *RS) const {
1559  unsigned i = 0;
1560  MachineInstr &MI = *II;
1561  MachineBasicBlock &MBB = *MI.getParent();
1562  MachineFunction &MF = *MBB.getParent();
1563  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1564  assert(!AFI->isThumb1OnlyFunction() &&
1565         "This eliminateFrameIndex does not support Thumb1!");
1566
1567  while (!MI.getOperand(i).isFI()) {
1568    ++i;
1569    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1570  }
1571
1572  int FrameIndex = MI.getOperand(i).getIndex();
1573  unsigned FrameReg;
1574
1575  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1576
1577  // Special handling of dbg_value instructions.
1578  if (MI.isDebugValue()) {
1579    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1580    MI.getOperand(i+1).ChangeToImmediate(Offset);
1581    return;
1582  }
1583
1584  // Modify MI as necessary to handle as much of 'Offset' as possible
1585  bool Done = false;
1586  if (!AFI->isThumbFunction())
1587    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1588  else {
1589    assert(AFI->isThumb2Function());
1590    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1591  }
1592  if (Done)
1593    return;
1594
1595  // If we get here, the immediate doesn't fit into the instruction.  We folded
1596  // as much as possible above, handle the rest, providing a register that is
1597  // SP+LargeImm.
1598  assert((Offset ||
1599          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1600          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1601         "This code isn't needed if offset already handled!");
1602
1603  unsigned ScratchReg = 0;
1604  int PIdx = MI.findFirstPredOperandIdx();
1605  ARMCC::CondCodes Pred = (PIdx == -1)
1606    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1607  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1608  if (Offset == 0)
1609    // Must be addrmode4/6.
1610    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1611  else {
1612    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1613    if (!AFI->isThumbFunction())
1614      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1615                              Offset, Pred, PredReg, TII);
1616    else {
1617      assert(AFI->isThumb2Function());
1618      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1619                             Offset, Pred, PredReg, TII);
1620    }
1621    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1622  }
1623}
1624
1625#include "ARMGenRegisterInfo.inc"
1626