ARMBaseRegisterInfo.cpp revision 5c33f5bf67f61e3a1addda6de735d28d550dd0eb 
1//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the base ARM implementation of TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMBaseRegisterInfo.h"
18#include "ARMInstrInfo.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMSubtarget.h"
21#include "llvm/Constants.h"
22#include "llvm/DerivedTypes.h"
23#include "llvm/Function.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineConstantPool.h"
26#include "llvm/CodeGen/MachineFrameInfo.h"
27#include "llvm/CodeGen/MachineFunction.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineLocation.h"
30#include "llvm/CodeGen/MachineRegisterInfo.h"
31#include "llvm/CodeGen/RegisterScavenging.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetFrameInfo.h"
36#include "llvm/Target/TargetMachine.h"
37#include "llvm/Target/TargetOptions.h"
38#include "llvm/ADT/BitVector.h"
39#include "llvm/ADT/SmallVector.h"
40#include "llvm/Support/CommandLine.h"
41
42namespace llvm {
43static cl::opt<bool>
44ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
45          cl::desc("Force use of virtual base registers for stack load/store"));
46static cl::opt<bool>
47EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
48          cl::desc("Enable pre-regalloc stack frame index allocation"));
49}
50
51using namespace llvm;
52
53unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
54                                                   bool *isSPVFP) {
55  if (isSPVFP)
56    *isSPVFP = false;
57
58  using namespace ARM;
59  switch (RegEnum) {
60  default:
61    llvm_unreachable("Unknown ARM register!");
62  case R0:  case D0:  case Q0:  return 0;
63  case R1:  case D1:  case Q1:  return 1;
64  case R2:  case D2:  case Q2:  return 2;
65  case R3:  case D3:  case Q3:  return 3;
66  case R4:  case D4:  case Q4:  return 4;
67  case R5:  case D5:  case Q5:  return 5;
68  case R6:  case D6:  case Q6:  return 6;
69  case R7:  case D7:  case Q7:  return 7;
70  case R8:  case D8:  case Q8:  return 8;
71  case R9:  case D9:  case Q9:  return 9;
72  case R10: case D10: case Q10: return 10;
73  case R11: case D11: case Q11: return 11;
74  case R12: case D12: case Q12: return 12;
75  case SP:  case D13: case Q13: return 13;
76  case LR:  case D14: case Q14: return 14;
77  case PC:  case D15: case Q15: return 15;
78
79  case D16: return 16;
80  case D17: return 17;
81  case D18: return 18;
82  case D19: return 19;
83  case D20: return 20;
84  case D21: return 21;
85  case D22: return 22;
86  case D23: return 23;
87  case D24: return 24;
88  case D25: return 25;
89  case D26: return 26;
90  case D27: return 27;
91  case D28: return 28;
92  case D29: return 29;
93  case D30: return 30;
94  case D31: return 31;
95
96  case S0: case S1: case S2: case S3:
97  case S4: case S5: case S6: case S7:
98  case S8: case S9: case S10: case S11:
99  case S12: case S13: case S14: case S15:
100  case S16: case S17: case S18: case S19:
101  case S20: case S21: case S22: case S23:
102  case S24: case S25: case S26: case S27:
103  case S28: case S29: case S30: case S31: {
104    if (isSPVFP)
105      *isSPVFP = true;
106    switch (RegEnum) {
107    default: return 0; // Avoid compile time warning.
108    case S0: return 0;
109    case S1: return 1;
110    case S2: return 2;
111    case S3: return 3;
112    case S4: return 4;
113    case S5: return 5;
114    case S6: return 6;
115    case S7: return 7;
116    case S8: return 8;
117    case S9: return 9;
118    case S10: return 10;
119    case S11: return 11;
120    case S12: return 12;
121    case S13: return 13;
122    case S14: return 14;
123    case S15: return 15;
124    case S16: return 16;
125    case S17: return 17;
126    case S18: return 18;
127    case S19: return 19;
128    case S20: return 20;
129    case S21: return 21;
130    case S22: return 22;
131    case S23: return 23;
132    case S24: return 24;
133    case S25: return 25;
134    case S26: return 26;
135    case S27: return 27;
136    case S28: return 28;
137    case S29: return 29;
138    case S30: return 30;
139    case S31: return 31;
140    }
141  }
142  }
143}
144
145ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
146                                         const ARMSubtarget &sti)
147  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
148    TII(tii), STI(sti),
149    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
150}
151
152const unsigned*
153ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
154  static const unsigned CalleeSavedRegs[] = {
155    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
156    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
157
158    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
159    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
160    0
161  };
162
163  static const unsigned DarwinCalleeSavedRegs[] = {
164    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
165    // register.
166    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
167    ARM::R11, ARM::R10, ARM::R8,
168
169    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
170    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
171    0
172  };
173  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
174}
175
176BitVector ARMBaseRegisterInfo::
177getReservedRegs(const MachineFunction &MF) const {
178  // FIXME: avoid re-calculating this everytime.
179  BitVector Reserved(getNumRegs());
180  Reserved.set(ARM::SP);
181  Reserved.set(ARM::PC);
182  Reserved.set(ARM::FPSCR);
183  if (hasFP(MF))
184    Reserved.set(FramePtr);
185  // Some targets reserve R9.
186  if (STI.isR9Reserved())
187    Reserved.set(ARM::R9);
188  return Reserved;
189}
190
191bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
192                                        unsigned Reg) const {
193  switch (Reg) {
194  default: break;
195  case ARM::SP:
196  case ARM::PC:
197    return true;
198  case ARM::R7:
199  case ARM::R11:
200    if (FramePtr == Reg && hasFP(MF))
201      return true;
202    break;
203  case ARM::R9:
204    return STI.isR9Reserved();
205  }
206
207  return false;
208}
209
210const TargetRegisterClass *
211ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
212                                              const TargetRegisterClass *B,
213                                              unsigned SubIdx) const {
214  switch (SubIdx) {
215  default: return 0;
216  case ARM::ssub_0:
217  case ARM::ssub_1:
218  case ARM::ssub_2:
219  case ARM::ssub_3: {
220    // S sub-registers.
221    if (A->getSize() == 8) {
222      if (B == &ARM::SPR_8RegClass)
223        return &ARM::DPR_8RegClass;
224      assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
225      if (A == &ARM::DPR_8RegClass)
226        return A;
227      return &ARM::DPR_VFP2RegClass;
228    }
229
230    if (A->getSize() == 16) {
231      if (B == &ARM::SPR_8RegClass)
232        return &ARM::QPR_8RegClass;
233      return &ARM::QPR_VFP2RegClass;
234    }
235
236    if (A->getSize() == 32) {
237      if (B == &ARM::SPR_8RegClass)
238        return 0;  // Do not allow coalescing!
239      return &ARM::QQPR_VFP2RegClass;
240    }
241
242    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
243    return 0;  // Do not allow coalescing!
244  }
245  case ARM::dsub_0:
246  case ARM::dsub_1:
247  case ARM::dsub_2:
248  case ARM::dsub_3: {
249    // D sub-registers.
250    if (A->getSize() == 16) {
251      if (B == &ARM::DPR_VFP2RegClass)
252        return &ARM::QPR_VFP2RegClass;
253      if (B == &ARM::DPR_8RegClass)
254        return 0;  // Do not allow coalescing!
255      return A;
256    }
257
258    if (A->getSize() == 32) {
259      if (B == &ARM::DPR_VFP2RegClass)
260        return &ARM::QQPR_VFP2RegClass;
261      if (B == &ARM::DPR_8RegClass)
262        return 0;  // Do not allow coalescing!
263      return A;
264    }
265
266    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
267    if (B != &ARM::DPRRegClass)
268      return 0;  // Do not allow coalescing!
269    return A;
270  }
271  case ARM::dsub_4:
272  case ARM::dsub_5:
273  case ARM::dsub_6:
274  case ARM::dsub_7: {
275    // D sub-registers of QQQQ registers.
276    if (A->getSize() == 64 && B == &ARM::DPRRegClass)
277      return A;
278    return 0;  // Do not allow coalescing!
279  }
280
281  case ARM::qsub_0:
282  case ARM::qsub_1: {
283    // Q sub-registers.
284    if (A->getSize() == 32) {
285      if (B == &ARM::QPR_VFP2RegClass)
286        return &ARM::QQPR_VFP2RegClass;
287      if (B == &ARM::QPR_8RegClass)
288        return 0;  // Do not allow coalescing!
289      return A;
290    }
291
292    assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
293    if (B == &ARM::QPRRegClass)
294      return A;
295    return 0;  // Do not allow coalescing!
296  }
297  case ARM::qsub_2:
298  case ARM::qsub_3: {
299    // Q sub-registers of QQQQ registers.
300    if (A->getSize() == 64 && B == &ARM::QPRRegClass)
301      return A;
302    return 0;  // Do not allow coalescing!
303  }
304  }
305  return 0;
306}
307
308bool
309ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
310                                          SmallVectorImpl<unsigned> &SubIndices,
311                                          unsigned &NewSubIdx) const {
312
313  unsigned Size = RC->getSize() * 8;
314  if (Size < 6)
315    return 0;
316
317  NewSubIdx = 0;  // Whole register.
318  unsigned NumRegs = SubIndices.size();
319  if (NumRegs == 8) {
320    // 8 D registers -> 1 QQQQ register.
321    return (Size == 512 &&
322            SubIndices[0] == ARM::dsub_0 &&
323            SubIndices[1] == ARM::dsub_1 &&
324            SubIndices[2] == ARM::dsub_2 &&
325            SubIndices[3] == ARM::dsub_3 &&
326            SubIndices[4] == ARM::dsub_4 &&
327            SubIndices[5] == ARM::dsub_5 &&
328            SubIndices[6] == ARM::dsub_6 &&
329            SubIndices[7] == ARM::dsub_7);
330  } else if (NumRegs == 4) {
331    if (SubIndices[0] == ARM::qsub_0) {
332      // 4 Q registers -> 1 QQQQ register.
333      return (Size == 512 &&
334              SubIndices[1] == ARM::qsub_1 &&
335              SubIndices[2] == ARM::qsub_2 &&
336              SubIndices[3] == ARM::qsub_3);
337    } else if (SubIndices[0] == ARM::dsub_0) {
338      // 4 D registers -> 1 QQ register.
339      if (Size >= 256 &&
340          SubIndices[1] == ARM::dsub_1 &&
341          SubIndices[2] == ARM::dsub_2 &&
342          SubIndices[3] == ARM::dsub_3) {
343        if (Size == 512)
344          NewSubIdx = ARM::qqsub_0;
345        return true;
346      }
347    } else if (SubIndices[0] == ARM::dsub_4) {
348      // 4 D registers -> 1 QQ register (2nd).
349      if (Size == 512 &&
350          SubIndices[1] == ARM::dsub_5 &&
351          SubIndices[2] == ARM::dsub_6 &&
352          SubIndices[3] == ARM::dsub_7) {
353        NewSubIdx = ARM::qqsub_1;
354        return true;
355      }
356    } else if (SubIndices[0] == ARM::ssub_0) {
357      // 4 S registers -> 1 Q register.
358      if (Size >= 128 &&
359          SubIndices[1] == ARM::ssub_1 &&
360          SubIndices[2] == ARM::ssub_2 &&
361          SubIndices[3] == ARM::ssub_3) {
362        if (Size >= 256)
363          NewSubIdx = ARM::qsub_0;
364        return true;
365      }
366    }
367  } else if (NumRegs == 2) {
368    if (SubIndices[0] == ARM::qsub_0) {
369      // 2 Q registers -> 1 QQ register.
370      if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
371        if (Size == 512)
372          NewSubIdx = ARM::qqsub_0;
373        return true;
374      }
375    } else if (SubIndices[0] == ARM::qsub_2) {
376      // 2 Q registers -> 1 QQ register (2nd).
377      if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
378        NewSubIdx = ARM::qqsub_1;
379        return true;
380      }
381    } else if (SubIndices[0] == ARM::dsub_0) {
382      // 2 D registers -> 1 Q register.
383      if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
384        if (Size >= 256)
385          NewSubIdx = ARM::qsub_0;
386        return true;
387      }
388    } else if (SubIndices[0] == ARM::dsub_2) {
389      // 2 D registers -> 1 Q register (2nd).
390      if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
391        NewSubIdx = ARM::qsub_1;
392        return true;
393      }
394    } else if (SubIndices[0] == ARM::dsub_4) {
395      // 2 D registers -> 1 Q register (3rd).
396      if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
397        NewSubIdx = ARM::qsub_2;
398        return true;
399      }
400    } else if (SubIndices[0] == ARM::dsub_6) {
401      // 2 D registers -> 1 Q register (3rd).
402      if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
403        NewSubIdx = ARM::qsub_3;
404        return true;
405      }
406    } else if (SubIndices[0] == ARM::ssub_0) {
407      // 2 S registers -> 1 D register.
408      if (SubIndices[1] == ARM::ssub_1) {
409        if (Size >= 128)
410          NewSubIdx = ARM::dsub_0;
411        return true;
412      }
413    } else if (SubIndices[0] == ARM::ssub_2) {
414      // 2 S registers -> 1 D register (2nd).
415      if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
416        NewSubIdx = ARM::dsub_1;
417        return true;
418      }
419    }
420  }
421  return false;
422}
423
424
425const TargetRegisterClass *
426ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
427  return ARM::GPRRegisterClass;
428}
429
430/// getAllocationOrder - Returns the register allocation order for a specified
431/// register class in the form of a pair of TargetRegisterClass iterators.
432std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
433ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
434                                        unsigned HintType, unsigned HintReg,
435                                        const MachineFunction &MF) const {
436  // Alternative register allocation orders when favoring even / odd registers
437  // of register pairs.
438
439  // No FP, R9 is available.
440  static const unsigned GPREven1[] = {
441    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
442    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
443    ARM::R9, ARM::R11
444  };
445  static const unsigned GPROdd1[] = {
446    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
447    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
448    ARM::R8, ARM::R10
449  };
450
451  // FP is R7, R9 is available.
452  static const unsigned GPREven2[] = {
453    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
454    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
455    ARM::R9, ARM::R11
456  };
457  static const unsigned GPROdd2[] = {
458    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
459    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
460    ARM::R8, ARM::R10
461  };
462
463  // FP is R11, R9 is available.
464  static const unsigned GPREven3[] = {
465    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
466    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
467    ARM::R9
468  };
469  static const unsigned GPROdd3[] = {
470    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
471    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
472    ARM::R8
473  };
474
475  // No FP, R9 is not available.
476  static const unsigned GPREven4[] = {
477    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
478    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
479    ARM::R11
480  };
481  static const unsigned GPROdd4[] = {
482    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
483    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
484    ARM::R10
485  };
486
487  // FP is R7, R9 is not available.
488  static const unsigned GPREven5[] = {
489    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
490    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
491    ARM::R11
492  };
493  static const unsigned GPROdd5[] = {
494    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
495    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
496    ARM::R10
497  };
498
499  // FP is R11, R9 is not available.
500  static const unsigned GPREven6[] = {
501    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
502    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
503  };
504  static const unsigned GPROdd6[] = {
505    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
506    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
507  };
508
509
510  if (HintType == ARMRI::RegPairEven) {
511    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
512      // It's no longer possible to fulfill this hint. Return the default
513      // allocation order.
514      return std::make_pair(RC->allocation_order_begin(MF),
515                            RC->allocation_order_end(MF));
516
517    if (!hasFP(MF)) {
518      if (!STI.isR9Reserved())
519        return std::make_pair(GPREven1,
520                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
521      else
522        return std::make_pair(GPREven4,
523                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
524    } else if (FramePtr == ARM::R7) {
525      if (!STI.isR9Reserved())
526        return std::make_pair(GPREven2,
527                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
528      else
529        return std::make_pair(GPREven5,
530                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
531    } else { // FramePtr == ARM::R11
532      if (!STI.isR9Reserved())
533        return std::make_pair(GPREven3,
534                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
535      else
536        return std::make_pair(GPREven6,
537                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
538    }
539  } else if (HintType == ARMRI::RegPairOdd) {
540    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
541      // It's no longer possible to fulfill this hint. Return the default
542      // allocation order.
543      return std::make_pair(RC->allocation_order_begin(MF),
544                            RC->allocation_order_end(MF));
545
546    if (!hasFP(MF)) {
547      if (!STI.isR9Reserved())
548        return std::make_pair(GPROdd1,
549                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
550      else
551        return std::make_pair(GPROdd4,
552                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
553    } else if (FramePtr == ARM::R7) {
554      if (!STI.isR9Reserved())
555        return std::make_pair(GPROdd2,
556                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
557      else
558        return std::make_pair(GPROdd5,
559                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
560    } else { // FramePtr == ARM::R11
561      if (!STI.isR9Reserved())
562        return std::make_pair(GPROdd3,
563                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
564      else
565        return std::make_pair(GPROdd6,
566                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
567    }
568  }
569  return std::make_pair(RC->allocation_order_begin(MF),
570                        RC->allocation_order_end(MF));
571}
572
573/// ResolveRegAllocHint - Resolves the specified register allocation hint
574/// to a physical register. Returns the physical register if it is successful.
575unsigned
576ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
577                                         const MachineFunction &MF) const {
578  if (Reg == 0 || !isPhysicalRegister(Reg))
579    return 0;
580  if (Type == 0)
581    return Reg;
582  else if (Type == (unsigned)ARMRI::RegPairOdd)
583    // Odd register.
584    return getRegisterPairOdd(Reg, MF);
585  else if (Type == (unsigned)ARMRI::RegPairEven)
586    // Even register.
587    return getRegisterPairEven(Reg, MF);
588  return 0;
589}
590
591void
592ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
593                                        MachineFunction &MF) const {
594  MachineRegisterInfo *MRI = &MF.getRegInfo();
595  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
596  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
597       Hint.first == (unsigned)ARMRI::RegPairEven) &&
598      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
599    // If 'Reg' is one of the even / odd register pair and it's now changed
600    // (e.g. coalesced) into a different register. The other register of the
601    // pair allocation hint must be updated to reflect the relationship
602    // change.
603    unsigned OtherReg = Hint.second;
604    Hint = MRI->getRegAllocationHint(OtherReg);
605    if (Hint.second == Reg)
606      // Make sure the pair has not already divorced.
607      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
608  }
609}
610
611/// hasFP - Return true if the specified function should have a dedicated frame
612/// pointer register.  This is true if the function has variable sized allocas
613/// or if frame pointer elimination is disabled.
614///
615bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
616  // Mac OS X requires FP not to be clobbered for backtracing purpose.
617  if (STI.isTargetDarwin())
618    return true;
619
620  const MachineFrameInfo *MFI = MF.getFrameInfo();
621  // Always eliminate non-leaf frame pointers.
622  return ((DisableFramePointerElim(MF) && MFI->hasCalls()) ||
623          needsStackRealignment(MF) ||
624          MFI->hasVarSizedObjects() ||
625          MFI->isFrameAddressTaken());
626}
627
628bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
629  const MachineFrameInfo *MFI = MF.getFrameInfo();
630  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
631  return (RealignStack &&
632          !AFI->isThumb1OnlyFunction() &&
633          !MFI->hasVarSizedObjects());
634}
635
636bool ARMBaseRegisterInfo::
637needsStackRealignment(const MachineFunction &MF) const {
638  const MachineFrameInfo *MFI = MF.getFrameInfo();
639  const Function *F = MF.getFunction();
640  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
641  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
642  bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
643                               F->hasFnAttr(Attribute::StackAlignment));
644
645  // FIXME: Currently we don't support stack realignment for functions with
646  //        variable-sized allocas.
647  // FIXME: It's more complicated than this...
648  if (0 && requiresRealignment && MFI->hasVarSizedObjects())
649    report_fatal_error(
650      "Stack realignment in presense of dynamic allocas is not supported");
651
652  // FIXME: This probably isn't the right place for this.
653  if (0 && requiresRealignment && AFI->isThumb1OnlyFunction())
654    report_fatal_error(
655      "Stack realignment in thumb1 functions is not supported");
656
657  return requiresRealignment && canRealignStack(MF);
658}
659
660bool ARMBaseRegisterInfo::
661cannotEliminateFrame(const MachineFunction &MF) const {
662  const MachineFrameInfo *MFI = MF.getFrameInfo();
663  if (DisableFramePointerElim(MF) && MFI->adjustsStack())
664    return true;
665  return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
666    || needsStackRealignment(MF);
667}
668
669/// estimateStackSize - Estimate and return the size of the frame.
670static unsigned estimateStackSize(MachineFunction &MF) {
671  const MachineFrameInfo *FFI = MF.getFrameInfo();
672  int Offset = 0;
673  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
674    int FixedOff = -FFI->getObjectOffset(i);
675    if (FixedOff > Offset) Offset = FixedOff;
676  }
677  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
678    if (FFI->isDeadObjectIndex(i))
679      continue;
680    Offset += FFI->getObjectSize(i);
681    unsigned Align = FFI->getObjectAlignment(i);
682    // Adjust to alignment boundary
683    Offset = (Offset+Align-1)/Align*Align;
684  }
685  return (unsigned)Offset;
686}
687
688/// estimateRSStackSizeLimit - Look at each instruction that references stack
689/// frames and return the stack size limit beyond which some of these
690/// instructions will require a scratch register during their expansion later.
691unsigned
692ARMBaseRegisterInfo::estimateRSStackSizeLimit(MachineFunction &MF) const {
693  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
694  unsigned Limit = (1 << 12) - 1;
695  for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) {
696    for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end();
697         I != E; ++I) {
698      for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) {
699        if (!I->getOperand(i).isFI()) continue;
700
701        // When using ADDri to get the address of a stack object, 255 is the
702        // largest offset guaranteed to fit in the immediate offset.
703        if (I->getOpcode() == ARM::ADDri) {
704          Limit = std::min(Limit, (1U << 8) - 1);
705          break;
706        }
707
708        // Otherwise check the addressing mode.
709        switch (I->getDesc().TSFlags & ARMII::AddrModeMask) {
710        case ARMII::AddrMode3:
711        case ARMII::AddrModeT2_i8:
712          Limit = std::min(Limit, (1U << 8) - 1);
713          break;
714        case ARMII::AddrMode5:
715        case ARMII::AddrModeT2_i8s4:
716          Limit = std::min(Limit, ((1U << 8) - 1) * 4);
717          break;
718        case ARMII::AddrModeT2_i12:
719          // i12 supports only positive offset so these will be converted to
720          // i8 opcodes. See llvm::rewriteT2FrameIndex.
721          if (hasFP(MF) && AFI->hasStackFrame())
722            Limit = std::min(Limit, (1U << 8) - 1);
723          break;
724        case ARMII::AddrMode6:
725          // Addressing mode 6 (load/store) instructions can't encode an
726          // immediate offset for stack references.
727          return 0;
728        default:
729          break;
730        }
731        break; // At most one FI per instruction
732      }
733    }
734  }
735
736  return Limit;
737}
738
739static unsigned GetFunctionSizeInBytes(const MachineFunction &MF,
740                                       const ARMBaseInstrInfo &TII) {
741  unsigned FnSize = 0;
742  for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end();
743       MBBI != E; ++MBBI) {
744    const MachineBasicBlock &MBB = *MBBI;
745    for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end();
746         I != E; ++I)
747      FnSize += TII.GetInstSizeInBytes(I);
748  }
749  return FnSize;
750}
751
752void
753ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
754                                                       RegScavenger *RS) const {
755  // This tells PEI to spill the FP as if it is any other callee-save register
756  // to take advantage the eliminateFrameIndex machinery. This also ensures it
757  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
758  // to combine multiple loads / stores.
759  bool CanEliminateFrame = true;
760  bool CS1Spilled = false;
761  bool LRSpilled = false;
762  unsigned NumGPRSpills = 0;
763  SmallVector<unsigned, 4> UnspilledCS1GPRs;
764  SmallVector<unsigned, 4> UnspilledCS2GPRs;
765  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
766  MachineFrameInfo *MFI = MF.getFrameInfo();
767
768  // Spill R4 if Thumb2 function requires stack realignment - it will be used as
769  // scratch register.
770  // FIXME: It will be better just to find spare register here.
771  if (needsStackRealignment(MF) &&
772      AFI->isThumb2Function())
773    MF.getRegInfo().setPhysRegUsed(ARM::R4);
774
775  // Spill LR if Thumb1 function uses variable length argument lists.
776  if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0)
777    MF.getRegInfo().setPhysRegUsed(ARM::LR);
778
779  // Don't spill FP if the frame can be eliminated. This is determined
780  // by scanning the callee-save registers to see if any is used.
781  const unsigned *CSRegs = getCalleeSavedRegs();
782  for (unsigned i = 0; CSRegs[i]; ++i) {
783    unsigned Reg = CSRegs[i];
784    bool Spilled = false;
785    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
786      AFI->setCSRegisterIsSpilled(Reg);
787      Spilled = true;
788      CanEliminateFrame = false;
789    } else {
790      // Check alias registers too.
791      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
792        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
793          Spilled = true;
794          CanEliminateFrame = false;
795        }
796      }
797    }
798
799    if (!ARM::GPRRegisterClass->contains(Reg))
800      continue;
801
802    if (Spilled) {
803      NumGPRSpills++;
804
805      if (!STI.isTargetDarwin()) {
806        if (Reg == ARM::LR)
807          LRSpilled = true;
808        CS1Spilled = true;
809        continue;
810      }
811
812      // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
813      switch (Reg) {
814      case ARM::LR:
815        LRSpilled = true;
816        // Fallthrough
817      case ARM::R4:
818      case ARM::R5:
819      case ARM::R6:
820      case ARM::R7:
821        CS1Spilled = true;
822        break;
823      default:
824        break;
825      }
826    } else {
827      if (!STI.isTargetDarwin()) {
828        UnspilledCS1GPRs.push_back(Reg);
829        continue;
830      }
831
832      switch (Reg) {
833      case ARM::R4:
834      case ARM::R5:
835      case ARM::R6:
836      case ARM::R7:
837      case ARM::LR:
838        UnspilledCS1GPRs.push_back(Reg);
839        break;
840      default:
841        UnspilledCS2GPRs.push_back(Reg);
842        break;
843      }
844    }
845  }
846
847  bool ForceLRSpill = false;
848  if (!LRSpilled && AFI->isThumb1OnlyFunction()) {
849    unsigned FnSize = GetFunctionSizeInBytes(MF, TII);
850    // Force LR to be spilled if the Thumb function size is > 2048. This enables
851    // use of BL to implement far jump. If it turns out that it's not needed
852    // then the branch fix up path will undo it.
853    if (FnSize >= (1 << 11)) {
854      CanEliminateFrame = false;
855      ForceLRSpill = true;
856    }
857  }
858
859  // If any of the stack slot references may be out of range of an immediate
860  // offset, make sure a register (or a spill slot) is available for the
861  // register scavenger. Note that if we're indexing off the frame pointer, the
862  // effective stack size is 4 bytes larger since the FP points to the stack
863  // slot of the previous FP. Also, if we have variable sized objects in the
864  // function, stack slot references will often be negative, and some of
865  // our instructions are positive-offset only, so conservatively consider
866  // that case to want a spill slot (or register) as well. Similarly, if
867  // the function adjusts the stack pointer during execution and the
868  // adjustments aren't already part of our stack size estimate, our offset
869  // calculations may be off, so be conservative.
870  // FIXME: We could add logic to be more precise about negative offsets
871  //        and which instructions will need a scratch register for them. Is it
872  //        worth the effort and added fragility?
873  bool BigStack =
874    (RS &&
875     (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >=
876      estimateRSStackSizeLimit(MF)))
877    || MFI->hasVarSizedObjects()
878    || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF));
879
880  bool ExtraCSSpill = false;
881  if (BigStack || !CanEliminateFrame || cannotEliminateFrame(MF)) {
882    AFI->setHasStackFrame(true);
883
884    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
885    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
886    if (!LRSpilled && CS1Spilled) {
887      MF.getRegInfo().setPhysRegUsed(ARM::LR);
888      AFI->setCSRegisterIsSpilled(ARM::LR);
889      NumGPRSpills++;
890      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
891                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
892      ForceLRSpill = false;
893      ExtraCSSpill = true;
894    }
895
896    if (hasFP(MF)) {
897      MF.getRegInfo().setPhysRegUsed(FramePtr);
898      NumGPRSpills++;
899    }
900
901    // If stack and double are 8-byte aligned and we are spilling an odd number
902    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
903    // the integer and double callee save areas.
904    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
905    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
906      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
907        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
908          unsigned Reg = UnspilledCS1GPRs[i];
909          // Don't spill high register if the function is thumb1
910          if (!AFI->isThumb1OnlyFunction() ||
911              isARMLowRegister(Reg) || Reg == ARM::LR) {
912            MF.getRegInfo().setPhysRegUsed(Reg);
913            AFI->setCSRegisterIsSpilled(Reg);
914            if (!isReservedReg(MF, Reg))
915              ExtraCSSpill = true;
916            break;
917          }
918        }
919      } else if (!UnspilledCS2GPRs.empty() &&
920                 !AFI->isThumb1OnlyFunction()) {
921        unsigned Reg = UnspilledCS2GPRs.front();
922        MF.getRegInfo().setPhysRegUsed(Reg);
923        AFI->setCSRegisterIsSpilled(Reg);
924        if (!isReservedReg(MF, Reg))
925          ExtraCSSpill = true;
926      }
927    }
928
929    // Estimate if we might need to scavenge a register at some point in order
930    // to materialize a stack offset. If so, either spill one additional
931    // callee-saved register or reserve a special spill slot to facilitate
932    // register scavenging. Thumb1 needs a spill slot for stack pointer
933    // adjustments also, even when the frame itself is small.
934    if (BigStack && !ExtraCSSpill) {
935      // If any non-reserved CS register isn't spilled, just spill one or two
936      // extra. That should take care of it!
937      unsigned NumExtras = TargetAlign / 4;
938      SmallVector<unsigned, 2> Extras;
939      while (NumExtras && !UnspilledCS1GPRs.empty()) {
940        unsigned Reg = UnspilledCS1GPRs.back();
941        UnspilledCS1GPRs.pop_back();
942        if (!isReservedReg(MF, Reg) &&
943            (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) ||
944             Reg == ARM::LR)) {
945          Extras.push_back(Reg);
946          NumExtras--;
947        }
948      }
949      // For non-Thumb1 functions, also check for hi-reg CS registers
950      if (!AFI->isThumb1OnlyFunction()) {
951        while (NumExtras && !UnspilledCS2GPRs.empty()) {
952          unsigned Reg = UnspilledCS2GPRs.back();
953          UnspilledCS2GPRs.pop_back();
954          if (!isReservedReg(MF, Reg)) {
955            Extras.push_back(Reg);
956            NumExtras--;
957          }
958        }
959      }
960      if (Extras.size() && NumExtras == 0) {
961        for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
962          MF.getRegInfo().setPhysRegUsed(Extras[i]);
963          AFI->setCSRegisterIsSpilled(Extras[i]);
964        }
965      } else if (!AFI->isThumb1OnlyFunction()) {
966        // note: Thumb1 functions spill to R12, not the stack.  Reserve a slot
967        // closest to SP or frame pointer.
968        const TargetRegisterClass *RC = ARM::GPRRegisterClass;
969        RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
970                                                           RC->getAlignment(),
971                                                           false));
972      }
973    }
974  }
975
976  if (ForceLRSpill) {
977    MF.getRegInfo().setPhysRegUsed(ARM::LR);
978    AFI->setCSRegisterIsSpilled(ARM::LR);
979    AFI->setLRIsSpilledForFarJump(true);
980  }
981}
982
983unsigned ARMBaseRegisterInfo::getRARegister() const {
984  return ARM::LR;
985}
986
987unsigned
988ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
989  if (hasFP(MF))
990    return FramePtr;
991  return ARM::SP;
992}
993
994// Provide a base+offset reference to an FI slot for debug info. It's the
995// same as what we use for resolving the code-gen references for now.
996// FIXME: This can go wrong when references are SP-relative and simple call
997//        frames aren't used.
998int
999ARMBaseRegisterInfo::getFrameIndexReference(const MachineFunction &MF, int FI,
1000                                            unsigned &FrameReg) const {
1001  return ResolveFrameIndexReference(MF, FI, FrameReg, 0);
1002}
1003
1004int
1005ARMBaseRegisterInfo::ResolveFrameIndexReference(const MachineFunction &MF,
1006                                                int FI,
1007                                                unsigned &FrameReg,
1008                                                int SPAdj) const {
1009  const MachineFrameInfo *MFI = MF.getFrameInfo();
1010  const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1011  int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize();
1012  int FPOffset = Offset - AFI->getFramePtrSpillOffset();
1013  bool isFixed = MFI->isFixedObjectIndex(FI);
1014
1015  FrameReg = ARM::SP;
1016  Offset += SPAdj;
1017  if (AFI->isGPRCalleeSavedArea1Frame(FI))
1018    return Offset - AFI->getGPRCalleeSavedArea1Offset();
1019  else if (AFI->isGPRCalleeSavedArea2Frame(FI))
1020    return Offset - AFI->getGPRCalleeSavedArea2Offset();
1021  else if (AFI->isDPRCalleeSavedAreaFrame(FI))
1022    return Offset - AFI->getDPRCalleeSavedAreaOffset();
1023
1024  // When dynamically realigning the stack, use the frame pointer for
1025  // parameters, and the stack pointer for locals.
1026  if (needsStackRealignment(MF)) {
1027    assert (hasFP(MF) && "dynamic stack realignment without a FP!");
1028    if (isFixed) {
1029      FrameReg = getFrameRegister(MF);
1030      Offset = FPOffset;
1031    }
1032    return Offset;
1033  }
1034
1035  // If there is a frame pointer, use it when we can.
1036  if (hasFP(MF) && AFI->hasStackFrame()) {
1037    // Use frame pointer to reference fixed objects. Use it for locals if
1038    // there are VLAs (and thus the SP isn't reliable as a base).
1039    if (isFixed || MFI->hasVarSizedObjects()) {
1040      FrameReg = getFrameRegister(MF);
1041      Offset = FPOffset;
1042    } else if (AFI->isThumb2Function()) {
1043      // In Thumb2 mode, the negative offset is very limited. Try to avoid
1044      // out of range references.
1045      if (FPOffset >= -255 && FPOffset < 0) {
1046        FrameReg = getFrameRegister(MF);
1047        Offset = FPOffset;
1048      }
1049    } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) {
1050      // Otherwise, use SP or FP, whichever is closer to the stack slot.
1051      FrameReg = getFrameRegister(MF);
1052      Offset = FPOffset;
1053    }
1054  }
1055  return Offset;
1056}
1057
1058int
1059ARMBaseRegisterInfo::getFrameIndexOffset(const MachineFunction &MF,
1060                                         int FI) const {
1061  unsigned FrameReg;
1062  return getFrameIndexReference(MF, FI, FrameReg);
1063}
1064
1065unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1066  llvm_unreachable("What is the exception register");
1067  return 0;
1068}
1069
1070unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1071  llvm_unreachable("What is the exception handler register");
1072  return 0;
1073}
1074
1075int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1076  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1077}
1078
1079unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1080                                              const MachineFunction &MF) const {
1081  switch (Reg) {
1082  default: break;
1083  // Return 0 if either register of the pair is a special register.
1084  // So no R12, etc.
1085  case ARM::R1:
1086    return ARM::R0;
1087  case ARM::R3:
1088    return ARM::R2;
1089  case ARM::R5:
1090    return ARM::R4;
1091  case ARM::R7:
1092    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
1093  case ARM::R9:
1094    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1095  case ARM::R11:
1096    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1097
1098  case ARM::S1:
1099    return ARM::S0;
1100  case ARM::S3:
1101    return ARM::S2;
1102  case ARM::S5:
1103    return ARM::S4;
1104  case ARM::S7:
1105    return ARM::S6;
1106  case ARM::S9:
1107    return ARM::S8;
1108  case ARM::S11:
1109    return ARM::S10;
1110  case ARM::S13:
1111    return ARM::S12;
1112  case ARM::S15:
1113    return ARM::S14;
1114  case ARM::S17:
1115    return ARM::S16;
1116  case ARM::S19:
1117    return ARM::S18;
1118  case ARM::S21:
1119    return ARM::S20;
1120  case ARM::S23:
1121    return ARM::S22;
1122  case ARM::S25:
1123    return ARM::S24;
1124  case ARM::S27:
1125    return ARM::S26;
1126  case ARM::S29:
1127    return ARM::S28;
1128  case ARM::S31:
1129    return ARM::S30;
1130
1131  case ARM::D1:
1132    return ARM::D0;
1133  case ARM::D3:
1134    return ARM::D2;
1135  case ARM::D5:
1136    return ARM::D4;
1137  case ARM::D7:
1138    return ARM::D6;
1139  case ARM::D9:
1140    return ARM::D8;
1141  case ARM::D11:
1142    return ARM::D10;
1143  case ARM::D13:
1144    return ARM::D12;
1145  case ARM::D15:
1146    return ARM::D14;
1147  case ARM::D17:
1148    return ARM::D16;
1149  case ARM::D19:
1150    return ARM::D18;
1151  case ARM::D21:
1152    return ARM::D20;
1153  case ARM::D23:
1154    return ARM::D22;
1155  case ARM::D25:
1156    return ARM::D24;
1157  case ARM::D27:
1158    return ARM::D26;
1159  case ARM::D29:
1160    return ARM::D28;
1161  case ARM::D31:
1162    return ARM::D30;
1163  }
1164
1165  return 0;
1166}
1167
1168unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1169                                             const MachineFunction &MF) const {
1170  switch (Reg) {
1171  default: break;
1172  // Return 0 if either register of the pair is a special register.
1173  // So no R12, etc.
1174  case ARM::R0:
1175    return ARM::R1;
1176  case ARM::R2:
1177    return ARM::R3;
1178  case ARM::R4:
1179    return ARM::R5;
1180  case ARM::R6:
1181    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
1182  case ARM::R8:
1183    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1184  case ARM::R10:
1185    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1186
1187  case ARM::S0:
1188    return ARM::S1;
1189  case ARM::S2:
1190    return ARM::S3;
1191  case ARM::S4:
1192    return ARM::S5;
1193  case ARM::S6:
1194    return ARM::S7;
1195  case ARM::S8:
1196    return ARM::S9;
1197  case ARM::S10:
1198    return ARM::S11;
1199  case ARM::S12:
1200    return ARM::S13;
1201  case ARM::S14:
1202    return ARM::S15;
1203  case ARM::S16:
1204    return ARM::S17;
1205  case ARM::S18:
1206    return ARM::S19;
1207  case ARM::S20:
1208    return ARM::S21;
1209  case ARM::S22:
1210    return ARM::S23;
1211  case ARM::S24:
1212    return ARM::S25;
1213  case ARM::S26:
1214    return ARM::S27;
1215  case ARM::S28:
1216    return ARM::S29;
1217  case ARM::S30:
1218    return ARM::S31;
1219
1220  case ARM::D0:
1221    return ARM::D1;
1222  case ARM::D2:
1223    return ARM::D3;
1224  case ARM::D4:
1225    return ARM::D5;
1226  case ARM::D6:
1227    return ARM::D7;
1228  case ARM::D8:
1229    return ARM::D9;
1230  case ARM::D10:
1231    return ARM::D11;
1232  case ARM::D12:
1233    return ARM::D13;
1234  case ARM::D14:
1235    return ARM::D15;
1236  case ARM::D16:
1237    return ARM::D17;
1238  case ARM::D18:
1239    return ARM::D19;
1240  case ARM::D20:
1241    return ARM::D21;
1242  case ARM::D22:
1243    return ARM::D23;
1244  case ARM::D24:
1245    return ARM::D25;
1246  case ARM::D26:
1247    return ARM::D27;
1248  case ARM::D28:
1249    return ARM::D29;
1250  case ARM::D30:
1251    return ARM::D31;
1252  }
1253
1254  return 0;
1255}
1256
1257/// emitLoadConstPool - Emits a load from constpool to materialize the
1258/// specified immediate.
1259void ARMBaseRegisterInfo::
1260emitLoadConstPool(MachineBasicBlock &MBB,
1261                  MachineBasicBlock::iterator &MBBI,
1262                  DebugLoc dl,
1263                  unsigned DestReg, unsigned SubIdx, int Val,
1264                  ARMCC::CondCodes Pred,
1265                  unsigned PredReg) const {
1266  MachineFunction &MF = *MBB.getParent();
1267  MachineConstantPool *ConstantPool = MF.getConstantPool();
1268  const Constant *C =
1269        ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
1270  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
1271
1272  BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
1273    .addReg(DestReg, getDefRegState(true), SubIdx)
1274    .addConstantPoolIndex(Idx)
1275    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
1276}
1277
1278bool ARMBaseRegisterInfo::
1279requiresRegisterScavenging(const MachineFunction &MF) const {
1280  return true;
1281}
1282
1283bool ARMBaseRegisterInfo::
1284requiresFrameIndexScavenging(const MachineFunction &MF) const {
1285  return true;
1286}
1287
1288bool ARMBaseRegisterInfo::
1289requiresVirtualBaseRegisters(const MachineFunction &MF) const {
1290  return EnableLocalStackAlloc;
1291}
1292
1293// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
1294// not required, we reserve argument space for call sites in the function
1295// immediately on entry to the current function. This eliminates the need for
1296// add/sub sp brackets around call sites. Returns true if the call frame is
1297// included as part of the stack frame.
1298bool ARMBaseRegisterInfo::
1299hasReservedCallFrame(const MachineFunction &MF) const {
1300  const MachineFrameInfo *FFI = MF.getFrameInfo();
1301  unsigned CFSize = FFI->getMaxCallFrameSize();
1302  // It's not always a good idea to include the call frame as part of the
1303  // stack frame. ARM (especially Thumb) has small immediate offset to
1304  // address the stack frame. So a large call frame can cause poor codegen
1305  // and may even makes it impossible to scavenge a register.
1306  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
1307    return false;
1308
1309  return !MF.getFrameInfo()->hasVarSizedObjects();
1310}
1311
1312// canSimplifyCallFramePseudos - If there is a reserved call frame, the
1313// call frame pseudos can be simplified. Unlike most targets, having a FP
1314// is not sufficient here since we still may reference some objects via SP
1315// even when FP is available in Thumb2 mode.
1316bool ARMBaseRegisterInfo::
1317canSimplifyCallFramePseudos(const MachineFunction &MF) const {
1318  return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects();
1319}
1320
1321static void
1322emitSPUpdate(bool isARM,
1323             MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
1324             DebugLoc dl, const ARMBaseInstrInfo &TII,
1325             int NumBytes,
1326             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
1327  if (isARM)
1328    emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1329                            Pred, PredReg, TII);
1330  else
1331    emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
1332                           Pred, PredReg, TII);
1333}
1334
1335
1336void ARMBaseRegisterInfo::
1337eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1338                              MachineBasicBlock::iterator I) const {
1339  if (!hasReservedCallFrame(MF)) {
1340    // If we have alloca, convert as follows:
1341    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
1342    // ADJCALLSTACKUP   -> add, sp, sp, amount
1343    MachineInstr *Old = I;
1344    DebugLoc dl = Old->getDebugLoc();
1345    unsigned Amount = Old->getOperand(0).getImm();
1346    if (Amount != 0) {
1347      // We need to keep the stack aligned properly.  To do this, we round the
1348      // amount of space needed for the outgoing arguments up to the next
1349      // alignment boundary.
1350      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1351      Amount = (Amount+Align-1)/Align*Align;
1352
1353      ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1354      assert(!AFI->isThumb1OnlyFunction() &&
1355             "This eliminateCallFramePseudoInstr does not support Thumb1!");
1356      bool isARM = !AFI->isThumbFunction();
1357
1358      // Replace the pseudo instruction with a new instruction...
1359      unsigned Opc = Old->getOpcode();
1360      int PIdx = Old->findFirstPredOperandIdx();
1361      ARMCC::CondCodes Pred = (PIdx == -1)
1362        ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
1363      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
1364        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
1365        unsigned PredReg = Old->getOperand(2).getReg();
1366        emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
1367      } else {
1368        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
1369        unsigned PredReg = Old->getOperand(3).getReg();
1370        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
1371        emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
1372      }
1373    }
1374  }
1375  MBB.erase(I);
1376}
1377
1378int64_t ARMBaseRegisterInfo::
1379getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
1380  const TargetInstrDesc &Desc = MI->getDesc();
1381  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1382  int64_t InstrOffs = 0;;
1383  int Scale = 1;
1384  unsigned ImmIdx = 0;
1385  switch (AddrMode) {
1386  case ARMII::AddrModeT2_i8:
1387  case ARMII::AddrModeT2_i12:
1388    // i8 supports only negative, and i12 supports only positive, so
1389    // based on Offset sign, consider the appropriate instruction
1390    InstrOffs = MI->getOperand(Idx+1).getImm();
1391    Scale = 1;
1392    break;
1393  case ARMII::AddrMode5: {
1394    // VFP address mode.
1395    const MachineOperand &OffOp = MI->getOperand(Idx+1);
1396    InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
1397    if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
1398      InstrOffs = -InstrOffs;
1399    Scale = 4;
1400    break;
1401  }
1402  case ARMII::AddrMode2: {
1403    ImmIdx = Idx+2;
1404    InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
1405    if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1406      InstrOffs = -InstrOffs;
1407    break;
1408  }
1409  case ARMII::AddrMode3: {
1410    ImmIdx = Idx+2;
1411    InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
1412    if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1413      InstrOffs = -InstrOffs;
1414    break;
1415  }
1416  case ARMII::AddrModeT1_s: {
1417    ImmIdx = Idx+1;
1418    InstrOffs = MI->getOperand(ImmIdx).getImm();
1419    Scale = 4;
1420    break;
1421  }
1422  default:
1423    llvm_unreachable("Unsupported addressing mode!");
1424    break;
1425  }
1426
1427  return InstrOffs * Scale;
1428}
1429
1430/// needsFrameBaseReg - Returns true if the instruction's frame index
1431/// reference would be better served by a base register other than FP
1432/// or SP. Used by LocalStackFrameAllocation to determine which frame index
1433/// references it should create new base registers for.
1434bool ARMBaseRegisterInfo::
1435needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
1436  for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
1437    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1438  }
1439
1440  // It's the load/store FI references that cause issues, as it can be difficult
1441  // to materialize the offset if it won't fit in the literal field. Estimate
1442  // based on the size of the local frame and some conservative assumptions
1443  // about the rest of the stack frame (note, this is pre-regalloc, so
1444  // we don't know everything for certain yet) whether this offset is likely
1445  // to be out of range of the immediate. Return true if so.
1446
1447  // We only generate virtual base registers for loads and stores, so
1448  // return false for everything else.
1449  unsigned Opc = MI->getOpcode();
1450  switch (Opc) {
1451  case ARM::LDR: case ARM::LDRH: case ARM::LDRB:
1452  case ARM::STR: case ARM::STRH: case ARM::STRB:
1453  case ARM::t2LDRi12: case ARM::t2LDRi8:
1454  case ARM::t2STRi12: case ARM::t2STRi8:
1455  case ARM::VLDRS: case ARM::VLDRD:
1456  case ARM::VSTRS: case ARM::VSTRD:
1457  case ARM::tSTRspi: case ARM::tLDRspi:
1458    if (ForceAllBaseRegAlloc)
1459      return true;
1460    break;
1461  default:
1462    return false;
1463  }
1464
1465  // Without a virtual base register, if the function has variable sized
1466  // objects, all fixed-size local references will be via the frame pointer,
1467  // Approximate the offset and see if it's legal for the instruction.
1468  // Note that the incoming offset is based on the SP value at function entry,
1469  // so it'll be negative.
1470  MachineFunction &MF = *MI->getParent()->getParent();
1471  MachineFrameInfo *MFI = MF.getFrameInfo();
1472  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1473
1474  // Estimate an offset from the frame pointer.
1475  // Conservatively assume all callee-saved registers get pushed. R4-R6
1476  // will be earlier than the FP, so we ignore those.
1477  // R7, LR
1478  int64_t FPOffset = Offset - 8;
1479  // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
1480  if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
1481    FPOffset -= 80;
1482  // Estimate an offset from the stack pointer.
1483  // The incoming offset is relating to the SP at the start of the function,
1484  // but when we access the local it'll be relative to the SP after local
1485  // allocation, so adjust our SP-relative offset by that allocation size.
1486  Offset = -Offset;
1487  Offset += MFI->getLocalFrameSize();
1488  // Assume that we'll have at least some spill slots allocated.
1489  // FIXME: This is a total SWAG number. We should run some statistics
1490  //        and pick a real one.
1491  Offset += 128; // 128 bytes of spill slots
1492
1493  // If there is a frame pointer, try using it.
1494  // The FP is only available if there is no dynamic realignment. We
1495  // don't know for sure yet whether we'll need that, so we guess based
1496  // on whether there are any local variables that would trigger it.
1497  unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
1498  if (hasFP(MF) &&
1499      !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
1500    if (isFrameOffsetLegal(MI, FPOffset))
1501      return false;
1502  }
1503  // If we can reference via the stack pointer, try that.
1504  // FIXME: This (and the code that resolves the references) can be improved
1505  //        to only disallow SP relative references in the live range of
1506  //        the VLA(s). In practice, it's unclear how much difference that
1507  //        would make, but it may be worth doing.
1508  if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
1509    return false;
1510
1511  // The offset likely isn't legal, we want to allocate a virtual base register.
1512  return true;
1513}
1514
1515/// materializeFrameBaseRegister - Insert defining instruction(s) for
1516/// BaseReg to be a pointer to FrameIdx before insertion point I.
1517void ARMBaseRegisterInfo::
1518materializeFrameBaseRegister(MachineBasicBlock::iterator I, unsigned BaseReg,
1519                             int FrameIdx, int64_t Offset) const {
1520  ARMFunctionInfo *AFI =
1521    I->getParent()->getParent()->getInfo<ARMFunctionInfo>();
1522  unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
1523    (AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
1524
1525  MachineInstrBuilder MIB =
1526    BuildMI(*I->getParent(), I, I->getDebugLoc(), TII.get(ADDriOpc), BaseReg)
1527    .addFrameIndex(FrameIdx).addImm(Offset);
1528  if (!AFI->isThumb1OnlyFunction())
1529    AddDefaultCC(AddDefaultPred(MIB));
1530}
1531
1532void
1533ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
1534                                       unsigned BaseReg, int64_t Offset) const {
1535  MachineInstr &MI = *I;
1536  MachineBasicBlock &MBB = *MI.getParent();
1537  MachineFunction &MF = *MBB.getParent();
1538  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1539  int Off = Offset; // ARM doesn't need the general 64-bit offsets
1540  unsigned i = 0;
1541
1542  assert(!AFI->isThumb1OnlyFunction() &&
1543         "This resolveFrameIndex does not support Thumb1!");
1544
1545  while (!MI.getOperand(i).isFI()) {
1546    ++i;
1547    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1548  }
1549  bool Done = false;
1550  if (!AFI->isThumbFunction())
1551    Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
1552  else {
1553    assert(AFI->isThumb2Function());
1554    Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
1555  }
1556  assert (Done && "Unable to resolve frame index!");
1557}
1558
1559bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
1560                                             int64_t Offset) const {
1561  const TargetInstrDesc &Desc = MI->getDesc();
1562  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1563  unsigned i = 0;
1564
1565  while (!MI->getOperand(i).isFI()) {
1566    ++i;
1567    assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
1568  }
1569
1570  // AddrMode4 and AddrMode6 cannot handle any offset.
1571  if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
1572    return Offset == 0;
1573
1574  unsigned NumBits = 0;
1575  unsigned Scale = 1;
1576  bool isSigned = true;
1577  switch (AddrMode) {
1578  case ARMII::AddrModeT2_i8:
1579  case ARMII::AddrModeT2_i12:
1580    // i8 supports only negative, and i12 supports only positive, so
1581    // based on Offset sign, consider the appropriate instruction
1582    Scale = 1;
1583    if (Offset < 0) {
1584      NumBits = 8;
1585      Offset = -Offset;
1586    } else {
1587      NumBits = 12;
1588    }
1589    break;
1590  case ARMII::AddrMode5:
1591    // VFP address mode.
1592    NumBits = 8;
1593    Scale = 4;
1594    break;
1595  case ARMII::AddrMode2:
1596    NumBits = 12;
1597    break;
1598  case ARMII::AddrMode3:
1599    NumBits = 8;
1600    break;
1601  case ARMII::AddrModeT1_s:
1602    NumBits = 5;
1603    Scale = 4;
1604    isSigned = false;
1605    break;
1606  default:
1607    llvm_unreachable("Unsupported addressing mode!");
1608    break;
1609  }
1610
1611  Offset += getFrameIndexInstrOffset(MI, i);
1612  // Make sure the offset is encodable for instructions that scale the
1613  // immediate.
1614  if ((Offset & (Scale-1)) != 0)
1615    return false;
1616
1617  if (isSigned && Offset < 0)
1618    Offset = -Offset;
1619
1620  unsigned Mask = (1 << NumBits) - 1;
1621  if ((unsigned)Offset <= Mask * Scale)
1622    return true;
1623
1624  return false;
1625}
1626
1627void
1628ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1629                                         int SPAdj, RegScavenger *RS) const {
1630  unsigned i = 0;
1631  MachineInstr &MI = *II;
1632  MachineBasicBlock &MBB = *MI.getParent();
1633  MachineFunction &MF = *MBB.getParent();
1634  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1635  assert(!AFI->isThumb1OnlyFunction() &&
1636         "This eliminateFrameIndex does not support Thumb1!");
1637
1638  while (!MI.getOperand(i).isFI()) {
1639    ++i;
1640    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1641  }
1642
1643  int FrameIndex = MI.getOperand(i).getIndex();
1644  unsigned FrameReg;
1645
1646  int Offset = ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
1647
1648  // Special handling of dbg_value instructions.
1649  if (MI.isDebugValue()) {
1650    MI.getOperand(i).  ChangeToRegister(FrameReg, false /*isDef*/);
1651    MI.getOperand(i+1).ChangeToImmediate(Offset);
1652    return;
1653  }
1654
1655  // Modify MI as necessary to handle as much of 'Offset' as possible
1656  bool Done = false;
1657  if (!AFI->isThumbFunction())
1658    Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
1659  else {
1660    assert(AFI->isThumb2Function());
1661    Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
1662  }
1663  if (Done)
1664    return;
1665
1666  // If we get here, the immediate doesn't fit into the instruction.  We folded
1667  // as much as possible above, handle the rest, providing a register that is
1668  // SP+LargeImm.
1669  assert((Offset ||
1670          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
1671          (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
1672         "This code isn't needed if offset already handled!");
1673
1674  unsigned ScratchReg = 0;
1675  int PIdx = MI.findFirstPredOperandIdx();
1676  ARMCC::CondCodes Pred = (PIdx == -1)
1677    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1678  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1679  if (Offset == 0)
1680    // Must be addrmode4/6.
1681    MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
1682  else {
1683    ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1684    if (!AFI->isThumbFunction())
1685      emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1686                              Offset, Pred, PredReg, TII);
1687    else {
1688      assert(AFI->isThumb2Function());
1689      emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
1690                             Offset, Pred, PredReg, TII);
1691    }
1692    MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1693  }
1694}
1695
1696/// Move iterator past the next bunch of callee save load / store ops for
1697/// the particular spill area (1: integer area 1, 2: integer area 2,
1698/// 3: fp area, 0: don't care).
1699static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1700                                   MachineBasicBlock::iterator &MBBI,
1701                                   int Opc1, int Opc2, unsigned Area,
1702                                   const ARMSubtarget &STI) {
1703  while (MBBI != MBB.end() &&
1704         ((MBBI->getOpcode() == Opc1) || (MBBI->getOpcode() == Opc2)) &&
1705         MBBI->getOperand(1).isFI()) {
1706    if (Area != 0) {
1707      bool Done = false;
1708      unsigned Category = 0;
1709      switch (MBBI->getOperand(0).getReg()) {
1710      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1711      case ARM::LR:
1712        Category = 1;
1713        break;
1714      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1715        Category = STI.isTargetDarwin() ? 2 : 1;
1716        break;
1717      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1718      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1719        Category = 3;
1720        break;
1721      default:
1722        Done = true;
1723        break;
1724      }
1725      if (Done || Category != Area)
1726        break;
1727    }
1728
1729    ++MBBI;
1730  }
1731}
1732
1733void ARMBaseRegisterInfo::
1734emitPrologue(MachineFunction &MF) const {
1735  MachineBasicBlock &MBB = MF.front();
1736  MachineBasicBlock::iterator MBBI = MBB.begin();
1737  MachineFrameInfo  *MFI = MF.getFrameInfo();
1738  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1739  assert(!AFI->isThumb1OnlyFunction() &&
1740         "This emitPrologue does not support Thumb1!");
1741  bool isARM = !AFI->isThumbFunction();
1742  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1743  unsigned NumBytes = MFI->getStackSize();
1744  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1745  DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1746
1747  // Determine the sizes of each callee-save spill areas and record which frame
1748  // belongs to which callee-save spill areas.
1749  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1750  int FramePtrSpillFI = 0;
1751
1752  // Allocate the vararg register save area. This is not counted in NumBytes.
1753  if (VARegSaveSize)
1754    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize);
1755
1756  if (!AFI->hasStackFrame()) {
1757    if (NumBytes != 0)
1758      emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1759    return;
1760  }
1761
1762  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1763    unsigned Reg = CSI[i].getReg();
1764    int FI = CSI[i].getFrameIdx();
1765    switch (Reg) {
1766    case ARM::R4:
1767    case ARM::R5:
1768    case ARM::R6:
1769    case ARM::R7:
1770    case ARM::LR:
1771      if (Reg == FramePtr)
1772        FramePtrSpillFI = FI;
1773      AFI->addGPRCalleeSavedArea1Frame(FI);
1774      GPRCS1Size += 4;
1775      break;
1776    case ARM::R8:
1777    case ARM::R9:
1778    case ARM::R10:
1779    case ARM::R11:
1780      if (Reg == FramePtr)
1781        FramePtrSpillFI = FI;
1782      if (STI.isTargetDarwin()) {
1783        AFI->addGPRCalleeSavedArea2Frame(FI);
1784        GPRCS2Size += 4;
1785      } else {
1786        AFI->addGPRCalleeSavedArea1Frame(FI);
1787        GPRCS1Size += 4;
1788      }
1789      break;
1790    default:
1791      AFI->addDPRCalleeSavedAreaFrame(FI);
1792      DPRCSSize += 8;
1793    }
1794  }
1795
1796  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1797  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS1Size);
1798  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 1, STI);
1799
1800  // Set FP to point to the stack slot that contains the previous FP.
1801  // For Darwin, FP is R7, which has now been stored in spill area 1.
1802  // Otherwise, if this is not Darwin, all the callee-saved registers go
1803  // into spill area 1, including the FP in R11.  In either case, it is
1804  // now safe to emit this assignment.
1805  bool HasFP = hasFP(MF);
1806  if (HasFP) {
1807    unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri;
1808    MachineInstrBuilder MIB =
1809      BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
1810      .addFrameIndex(FramePtrSpillFI).addImm(0);
1811    AddDefaultCC(AddDefaultPred(MIB));
1812  }
1813
1814  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1815  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -GPRCS2Size);
1816
1817  // Build the new SUBri to adjust SP for FP callee-save spill area.
1818  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, ARM::t2STRi12, 2, STI);
1819  emitSPUpdate(isARM, MBB, MBBI, dl, TII, -DPRCSSize);
1820
1821  // Determine starting offsets of spill areas.
1822  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1823  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1824  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1825  if (HasFP)
1826    AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) +
1827                                NumBytes);
1828  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1829  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1830  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1831
1832  movePastCSLoadStoreOps(MBB, MBBI, ARM::VSTRD, 0, 3, STI);
1833  NumBytes = DPRCSOffset;
1834  if (NumBytes) {
1835    // Adjust SP after all the callee-save spills.
1836    emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes);
1837    if (HasFP)
1838      AFI->setShouldRestoreSPFromFP(true);
1839  }
1840
1841  if (STI.isTargetELF() && hasFP(MF)) {
1842    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1843                             AFI->getFramePtrSpillOffset());
1844    AFI->setShouldRestoreSPFromFP(true);
1845  }
1846
1847  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1848  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1849  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1850
1851  // If we need dynamic stack realignment, do it here.
1852  if (needsStackRealignment(MF)) {
1853    unsigned MaxAlign = MFI->getMaxAlignment();
1854    assert (!AFI->isThumb1OnlyFunction());
1855    if (!AFI->isThumbFunction()) {
1856      // Emit bic sp, sp, MaxAlign
1857      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1858                                          TII.get(ARM::BICri), ARM::SP)
1859                                  .addReg(ARM::SP, RegState::Kill)
1860                                  .addImm(MaxAlign-1)));
1861    } else {
1862      // We cannot use sp as source/dest register here, thus we're emitting the
1863      // following sequence:
1864      // mov r4, sp
1865      // bic r4, r4, MaxAlign
1866      // mov sp, r4
1867      // FIXME: It will be better just to find spare register here.
1868      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
1869        .addReg(ARM::SP, RegState::Kill);
1870      AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
1871                                          TII.get(ARM::t2BICri), ARM::R4)
1872                                  .addReg(ARM::R4, RegState::Kill)
1873                                  .addImm(MaxAlign-1)));
1874      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
1875        .addReg(ARM::R4, RegState::Kill);
1876    }
1877
1878    AFI->setShouldRestoreSPFromFP(true);
1879  }
1880
1881  // If the frame has variable sized objects then the epilogue must restore
1882  // the sp from fp.
1883  if (!AFI->shouldRestoreSPFromFP() && MFI->hasVarSizedObjects())
1884    AFI->setShouldRestoreSPFromFP(true);
1885}
1886
1887static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1888  for (unsigned i = 0; CSRegs[i]; ++i)
1889    if (Reg == CSRegs[i])
1890      return true;
1891  return false;
1892}
1893
1894static bool isCSRestore(MachineInstr *MI,
1895                        const ARMBaseInstrInfo &TII,
1896                        const unsigned *CSRegs) {
1897  return ((MI->getOpcode() == (int)ARM::VLDRD ||
1898           MI->getOpcode() == (int)ARM::LDR ||
1899           MI->getOpcode() == (int)ARM::t2LDRi12) &&
1900          MI->getOperand(1).isFI() &&
1901          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1902}
1903
1904void ARMBaseRegisterInfo::
1905emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
1906  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1907  assert(MBBI->getDesc().isReturn() &&
1908         "Can only insert epilog into returning blocks");
1909  unsigned RetOpcode = MBBI->getOpcode();
1910  DebugLoc dl = MBBI->getDebugLoc();
1911  MachineFrameInfo *MFI = MF.getFrameInfo();
1912  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1913  assert(!AFI->isThumb1OnlyFunction() &&
1914         "This emitEpilogue does not support Thumb1!");
1915  bool isARM = !AFI->isThumbFunction();
1916
1917  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1918  int NumBytes = (int)MFI->getStackSize();
1919
1920  if (!AFI->hasStackFrame()) {
1921    if (NumBytes != 0)
1922      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1923  } else {
1924    // Unwind MBBI to point to first LDR / VLDRD.
1925    const unsigned *CSRegs = getCalleeSavedRegs();
1926    if (MBBI != MBB.begin()) {
1927      do
1928        --MBBI;
1929      while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs));
1930      if (!isCSRestore(MBBI, TII, CSRegs))
1931        ++MBBI;
1932    }
1933
1934    // Move SP to start of FP callee save spill area.
1935    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1936                 AFI->getGPRCalleeSavedArea2Size() +
1937                 AFI->getDPRCalleeSavedAreaSize());
1938
1939    // Reset SP based on frame pointer only if the stack frame extends beyond
1940    // frame pointer stack slot or target is ELF and the function has FP.
1941    if (AFI->shouldRestoreSPFromFP()) {
1942      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1943      if (NumBytes) {
1944        if (isARM)
1945          emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1946                                  ARMCC::AL, 0, TII);
1947        else
1948          emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes,
1949                                 ARMCC::AL, 0, TII);
1950      } else {
1951        // Thumb2 or ARM.
1952        if (isARM)
1953          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
1954            .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1955        else
1956          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
1957            .addReg(FramePtr);
1958      }
1959    } else if (NumBytes)
1960      emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
1961
1962    // Move SP to start of integer callee save spill area 2.
1963    movePastCSLoadStoreOps(MBB, MBBI, ARM::VLDRD, 0, 3, STI);
1964    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getDPRCalleeSavedAreaSize());
1965
1966    // Move SP to start of integer callee save spill area 1.
1967    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 2, STI);
1968    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea2Size());
1969
1970    // Move SP to SP upon entry to the function.
1971    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, ARM::t2LDRi12, 1, STI);
1972    emitSPUpdate(isARM, MBB, MBBI, dl, TII, AFI->getGPRCalleeSavedArea1Size());
1973  }
1974
1975  if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND ||
1976      RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) {
1977    // Tail call return: adjust the stack pointer and jump to callee.
1978    MBBI = prior(MBB.end());
1979    MachineOperand &JumpTarget = MBBI->getOperand(0);
1980
1981    // Jump to label or value in register.
1982    if (RetOpcode == ARM::TCRETURNdi) {
1983      BuildMI(MBB, MBBI, dl,
1984            TII.get(STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd)).
1985        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1986                         JumpTarget.getTargetFlags());
1987    } else if (RetOpcode == ARM::TCRETURNdiND) {
1988      BuildMI(MBB, MBBI, dl,
1989            TII.get(STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND)).
1990        addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1991                         JumpTarget.getTargetFlags());
1992    } else if (RetOpcode == ARM::TCRETURNri) {
1993      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)).
1994        addReg(JumpTarget.getReg(), RegState::Kill);
1995    } else if (RetOpcode == ARM::TCRETURNriND) {
1996      BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)).
1997        addReg(JumpTarget.getReg(), RegState::Kill);
1998    }
1999
2000    MachineInstr *NewMI = prior(MBBI);
2001    for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
2002      NewMI->addOperand(MBBI->getOperand(i));
2003
2004    // Delete the pseudo instruction TCRETURN.
2005    MBB.erase(MBBI);
2006  }
2007
2008  if (VARegSaveSize)
2009    emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize);
2010}
2011
2012#include "ARMGenRegisterInfo.inc"
2013