| 8647750dfbae36a7a49767202a2e363ffc861e5a |
|
16-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Add X86 code emitter support AVX encoded MRMDestReg instructions.
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 9d3f3c5f400578855f6f7b71670cb8514b4fac0f |
|
14-Mar-2013 |
Craig Topper <craig.topper@gmail.com> |
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
|
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 7abf67a092c0a75d6d1631766d6a8ef14e38d526 |
|
04-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add register encoding support in X86 backend
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 8a312fb3aaec90537d434a5cc41edf566ff80dca |
|
19-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 86a1c32e67b23c5e9e42dff9eb86e99ba15bb42f |
|
15-Sep-2012 |
Craig Topper <craig.topper@gmail.com> |
Use LLVM_DELETED_FUNCTION in place of 'DO NOT IMPLEMENT' comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 5aba78bd8056dc407bcbce4080ffcd12b13c7342 |
|
12-Jul-2012 |
Craig Topper <craig.topper@gmail.com> |
Update GATHER instructions to support 2 read-write operands. Patch from myself and Manman Ren.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160110 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 1f7a1b68a07ea6bdf521525a7928f4a8c5216713 |
|
26-Jun-2012 |
Manman Ren <mren@apple.com> |
X86: add GATHER intrinsics (AVX2) in LLVM
Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 177cf1e1a3685209ab805f82897902a8d2b61661 |
|
31-May-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 1386e9b7b16a8138ae7060c2dbb8b029f7c4fce2 |
|
29-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions.
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 5084c6b0a29ed409092bd31cd75849312a73bee5 |
|
19-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 918f55fe239f00651e396be841f2b3b6e242f98d |
|
15-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Allow MCCodeEmitter access to the target MCRegisterInfo.
Add the MCRegisterInfo to the factories and constructors.
Patch by Tom Stellard <Tom.Stellard@amd.com>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| d9e85ef08bdd41b285f77af6c95f5ec17b43c80a |
|
21-Mar-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Put Is64BitMemOperand into !defined(NDEBUG) for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153185 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 4fd3d292753bd8232a76d5ac6b107f5899e5bfaa |
|
21-Mar-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Fix generation of the address size override prefix. Add assertions for
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 28a713b20ad17f9a02d4677d8a2fea0edb208418 |
|
19-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add vmfunc instruction to X86 assembler and disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 9e3d0b335111b2df73984a6cfd9ef1cd5d323872 |
|
18-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| d4a19b6a72d19a6f90b676aac37118664b7b7a84 |
|
11-Feb-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add support for implicit TLS model used with MS VC runtime.
Patch by Kai Nacke!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 6d1263acb9704b38a8d90fd6ce94f49193cd4dde |
|
05-Feb-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert assert(0) to llvm_unreachable in X86 Target directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| cb5dca38157a48c734660746e7f7340d5db7c2db |
|
27-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Keep source location information for X86 MCFixup's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149106 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 5d1a38cbfac62f75ee22cc0c9195616ea5fe5553 |
|
30-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| ebebe35d1c5ad689caf31cdc4da5b7a9539ffa5c |
|
12-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
XOP encoding bits and logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| f3aefb56def210eb0c23ecb8f2e0bf7f4be78a37 |
|
10-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Handle expressions of the form _GLOBAL_OFFSET_TABLE_-symbol the same way gas
does. The _GLOBAL_OFFSET_TABLE_ is still magical in that we get a R_386_GOTPC,
but it doesn't change the immediate in the same way as when the expression
has no right hand side symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 703420f50e458e2482e55c9a5b3cafa0b734f507 |
|
08-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 1b9b377975b3f437acef8c2ba90de582add52f65 |
|
25-Nov-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
This patch contains support for encoding FMA4 instructions and
tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 75485d6746f8b5b23c17cf6d2364e7e1e0705992 |
|
23-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| ee62e4f6d192ee31d1ad9dd0ba0c41db6663d3c7 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 17730847d59c919d97f097d46a3fcba1888e5300 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 566f233ba64c0bb2773b5717cb18753c7564f4b7 |
|
15-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 4e423359721fa88cb50ccea51ccf1c520d765ad0 |
|
20-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Tidy up a bit more, fix tab and remove trailing whitespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 77169a919718b74f62ab6a577f65ac5ef9547aba |
|
20-Sep-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Tidy up code!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 0c9acfcb50a844eefe92556e59c81fc302f32d1c |
|
20-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Re-write part of VEX encoding logic, to be more easy to read! Also fix
a bug and add a testcase!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 863e0f25b7b53f6c7f43cdb8a0b900003096595e |
|
19-Aug-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
implementation!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138029 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| 5de728cfe1a922ac9b13546dca94526b2fa693b6 |
|
28-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| a44defeb2208376ca3113ffdddc391570ba865b8 |
|
27-Jul-2011 |
Jeffrey Yasskin <jyasskin@google.com> |
Explicitly cast narrowing conversions inside {}s that will become errors in
C++0x.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|
| a87e40f16f1c3117412e01107807e490d6fb29bc |
|
25-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
More refactoring.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
|