| 8dc741e400213ea8183e09626f0d1f45f14e044f |
|
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for
the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 763c858edeb76173ee4ef5ab9bf7d750db5d8c4f |
|
17-Feb-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 970a479c02a418726950580e13136acd2a2dc13f |
|
27-Jan-2013 |
Richard Osborne <richard@xmos.com> |
[XCore] Add missing l2rus instructions.
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| c47bd9899b639c3384268f871009259c2a94fba4 |
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25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l4r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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| 1f375e5bc78647f9b29564eafdc907250ccd91ed |
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25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Use the correct format in the STW / SETPSC instruction names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 3b6a5eefe0ab2199bc69094b390b736ae332b905 |
|
25-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b |
|
23-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 9b709f8b3f3fa6e9bfb5007b70e096f6192f3ef8 |
|
21-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encoding / disassembly support for ru6 / lru6 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| b853c415c663c752c669cb191cea95542c1d21f6 |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| c78ec6b6bc05572aed6af1eee4349d76a68ded18 |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l3r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| a68c64fbb2f1bee7f9313f3ee19c35677563f974 |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembler support for 2rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 62b8786d12ceacafd665d4a1fbb6e90af0ec368c |
|
20-Jan-2013 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| c47793c62c434bd27fee1d243c2081a34d4f3817 |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for l2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 6e43b7f6b20b39b041cf24d732ddb802bbd6471a |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Fix parameter name in prototypes in XCoreDisassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170332 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 35150cbf4166ae8d69032d355f1e8d83b4a6eb3c |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for rus instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 1ffe48a84b398e8cebbdc7a47bedb57e1e67e63f |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings / disassembly support for 2r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| b4d40a04f0639fdec8329a8708565411fa53b5bc |
|
17-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Update comments to match recommended doxygen style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 54d6266e9baa8c2796c4a95c35897b5c67d8d910 |
|
16-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add instruction encodings and disassembly for 1r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|
| 881e3cca66c64a57ff431a4f6d1136dd6017c137 |
|
16-Dec-2012 |
Richard Osborne <richard@xmos.com> |
Add XCore disassembler.
Currently there is no instruction encoding info and
XCoreDisassembler::getInstruction() always returns Fail. I intend to add
instruction encodings and tests in follow on commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
|