1//===- XCoreDisassembler.cpp - Disassembler for XCore -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9///
10/// \file
11/// \brief This file is part of the XCore Disassembler.
12///
13//===----------------------------------------------------------------------===//
14
15#include "XCore.h"
16#include "XCoreRegisterInfo.h"
17#include "llvm/MC/MCDisassembler.h"
18#include "llvm/MC/MCFixedLenDisassembler.h"
19#include "llvm/MC/MCInst.h"
20#include "llvm/MC/MCSubtargetInfo.h"
21#include "llvm/Support/MemoryObject.h"
22#include "llvm/Support/TargetRegistry.h"
23
24using namespace llvm;
25
26typedef MCDisassembler::DecodeStatus DecodeStatus;
27
28namespace {
29
30/// \brief A disassembler class for XCore.
31class XCoreDisassembler : public MCDisassembler {
32  const MCRegisterInfo *RegInfo;
33public:
34  XCoreDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info) :
35    MCDisassembler(STI), RegInfo(Info) {}
36
37  /// \brief See MCDisassembler.
38  virtual DecodeStatus getInstruction(MCInst &instr,
39                                      uint64_t &size,
40                                      const MemoryObject &region,
41                                      uint64_t address,
42                                      raw_ostream &vStream,
43                                      raw_ostream &cStream) const;
44
45  const MCRegisterInfo *getRegInfo() const { return RegInfo; }
46};
47}
48
49static bool readInstruction16(const MemoryObject &region,
50                              uint64_t address,
51                              uint64_t &size,
52                              uint16_t &insn) {
53  uint8_t Bytes[4];
54
55  // We want to read exactly 2 Bytes of data.
56  if (region.readBytes(address, 2, Bytes, NULL) == -1) {
57    size = 0;
58    return false;
59  }
60  // Encoded as a little-endian 16-bit word in the stream.
61  insn = (Bytes[0] <<  0) | (Bytes[1] <<  8);
62  return true;
63}
64
65static bool readInstruction32(const MemoryObject &region,
66                              uint64_t address,
67                              uint64_t &size,
68                              uint32_t &insn) {
69  uint8_t Bytes[4];
70
71  // We want to read exactly 4 Bytes of data.
72  if (region.readBytes(address, 4, Bytes, NULL) == -1) {
73    size = 0;
74    return false;
75  }
76  // Encoded as a little-endian 32-bit word in the stream.
77  insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
78         (Bytes[3] << 24);
79  return true;
80}
81
82static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
83  const XCoreDisassembler *Dis = static_cast<const XCoreDisassembler*>(D);
84  return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
85}
86
87static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
88                                              unsigned RegNo,
89                                              uint64_t Address,
90                                              const void *Decoder);
91
92static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
93                                      uint64_t Address, const void *Decoder);
94
95static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
96                                       uint64_t Address, const void *Decoder);
97
98static DecodeStatus Decode2RInstruction(MCInst &Inst,
99                                        unsigned Insn,
100                                        uint64_t Address,
101                                        const void *Decoder);
102
103static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
104                                           unsigned Insn,
105                                           uint64_t Address,
106                                           const void *Decoder);
107
108static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
109                                         unsigned Insn,
110                                         uint64_t Address,
111                                         const void *Decoder);
112
113static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
114                                              unsigned Insn,
115                                              uint64_t Address,
116                                              const void *Decoder);
117
118static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
119                                         unsigned Insn,
120                                         uint64_t Address,
121                                         const void *Decoder);
122
123static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
124                                             unsigned Insn,
125                                             uint64_t Address,
126                                             const void *Decoder);
127
128static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
129                                                   unsigned Insn,
130                                                   uint64_t Address,
131                                                   const void *Decoder);
132
133static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
134                                         unsigned Insn,
135                                         uint64_t Address,
136                                         const void *Decoder);
137
138static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
139                                          unsigned Insn,
140                                          uint64_t Address,
141                                          const void *Decoder);
142
143static DecodeStatus Decode3RInstruction(MCInst &Inst,
144                                        unsigned Insn,
145                                        uint64_t Address,
146                                        const void *Decoder);
147
148static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
149                                           unsigned Insn,
150                                           uint64_t Address,
151                                           const void *Decoder);
152
153static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
154                                          unsigned Insn,
155                                          uint64_t Address,
156                                          const void *Decoder);
157
158static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
159                                              unsigned Insn,
160                                              uint64_t Address,
161                                              const void *Decoder);
162
163static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
164                                         unsigned Insn,
165                                         uint64_t Address,
166                                         const void *Decoder);
167
168static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
169                                               unsigned Insn,
170                                               uint64_t Address,
171                                               const void *Decoder);
172
173static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
174                                           unsigned Insn,
175                                           uint64_t Address,
176                                           const void *Decoder);
177
178static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
179                                               unsigned Insn,
180                                               uint64_t Address,
181                                               const void *Decoder);
182
183static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
184                                         unsigned Insn,
185                                         uint64_t Address,
186                                         const void *Decoder);
187
188static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
189                                         unsigned Insn,
190                                         uint64_t Address,
191                                         const void *Decoder);
192
193static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
194                                               unsigned Insn,
195                                               uint64_t Address,
196                                               const void *Decoder);
197
198static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
199                                                     unsigned Insn,
200                                                     uint64_t Address,
201                                                     const void *Decoder);
202
203#include "XCoreGenDisassemblerTables.inc"
204
205static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
206                                              unsigned RegNo,
207                                              uint64_t Address,
208                                              const void *Decoder)
209{
210  if (RegNo > 11)
211    return MCDisassembler::Fail;
212  unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
213  Inst.addOperand(MCOperand::CreateReg(Reg));
214  return MCDisassembler::Success;
215}
216
217static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
218                                      uint64_t Address, const void *Decoder) {
219  if (Val > 11)
220    return MCDisassembler::Fail;
221  static unsigned Values[] = {
222    32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
223  };
224  Inst.addOperand(MCOperand::CreateImm(Values[Val]));
225  return MCDisassembler::Success;
226}
227
228static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
229                                       uint64_t Address, const void *Decoder) {
230  Inst.addOperand(MCOperand::CreateImm(Val));
231  Inst.addOperand(MCOperand::CreateImm(0));
232  return MCDisassembler::Success;
233}
234
235static DecodeStatus
236Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
237  unsigned Combined = fieldFromInstruction(Insn, 6, 5);
238  if (Combined < 27)
239    return MCDisassembler::Fail;
240  if (fieldFromInstruction(Insn, 5, 1)) {
241    if (Combined == 31)
242      return MCDisassembler::Fail;
243    Combined += 5;
244  }
245  Combined -= 27;
246  unsigned Op1High = Combined % 3;
247  unsigned Op2High = Combined / 3;
248  Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 2, 2);
249  Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
250  return MCDisassembler::Success;
251}
252
253static DecodeStatus
254Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
255                     unsigned &Op3) {
256  unsigned Combined = fieldFromInstruction(Insn, 6, 5);
257  if (Combined >= 27)
258    return MCDisassembler::Fail;
259
260  unsigned Op1High = Combined % 3;
261  unsigned Op2High = (Combined / 3) % 3;
262  unsigned Op3High = Combined / 9;
263  Op1 = (Op1High << 2) | fieldFromInstruction(Insn, 4, 2);
264  Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
265  Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2);
266  return MCDisassembler::Success;
267}
268
269static DecodeStatus
270Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
271                         const void *Decoder) {
272  // Try and decode as a 3R instruction.
273  unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
274  switch (Opcode) {
275  case 0x0:
276    Inst.setOpcode(XCore::STW_2rus);
277    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
278  case 0x1:
279    Inst.setOpcode(XCore::LDW_2rus);
280    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
281  case 0x2:
282    Inst.setOpcode(XCore::ADD_3r);
283    return Decode3RInstruction(Inst, Insn, Address, Decoder);
284  case 0x3:
285    Inst.setOpcode(XCore::SUB_3r);
286    return Decode3RInstruction(Inst, Insn, Address, Decoder);
287  case 0x4:
288    Inst.setOpcode(XCore::SHL_3r);
289    return Decode3RInstruction(Inst, Insn, Address, Decoder);
290  case 0x5:
291    Inst.setOpcode(XCore::SHR_3r);
292    return Decode3RInstruction(Inst, Insn, Address, Decoder);
293  case 0x6:
294    Inst.setOpcode(XCore::EQ_3r);
295    return Decode3RInstruction(Inst, Insn, Address, Decoder);
296  case 0x7:
297    Inst.setOpcode(XCore::AND_3r);
298    return Decode3RInstruction(Inst, Insn, Address, Decoder);
299  case 0x8:
300    Inst.setOpcode(XCore::OR_3r);
301    return Decode3RInstruction(Inst, Insn, Address, Decoder);
302  case 0x9:
303    Inst.setOpcode(XCore::LDW_3r);
304    return Decode3RInstruction(Inst, Insn, Address, Decoder);
305  case 0x10:
306    Inst.setOpcode(XCore::LD16S_3r);
307    return Decode3RInstruction(Inst, Insn, Address, Decoder);
308  case 0x11:
309    Inst.setOpcode(XCore::LD8U_3r);
310    return Decode3RInstruction(Inst, Insn, Address, Decoder);
311  case 0x12:
312    Inst.setOpcode(XCore::ADD_2rus);
313    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
314  case 0x13:
315    Inst.setOpcode(XCore::SUB_2rus);
316    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
317  case 0x14:
318    Inst.setOpcode(XCore::SHL_2rus);
319    return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
320  case 0x15:
321    Inst.setOpcode(XCore::SHR_2rus);
322    return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
323  case 0x16:
324    Inst.setOpcode(XCore::EQ_2rus);
325    return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
326  case 0x17:
327    Inst.setOpcode(XCore::TSETR_3r);
328    return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
329  case 0x18:
330    Inst.setOpcode(XCore::LSS_3r);
331    return Decode3RInstruction(Inst, Insn, Address, Decoder);
332  case 0x19:
333    Inst.setOpcode(XCore::LSU_3r);
334    return Decode3RInstruction(Inst, Insn, Address, Decoder);
335  }
336  return MCDisassembler::Fail;
337}
338
339static DecodeStatus
340Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
341                    const void *Decoder) {
342  unsigned Op1, Op2;
343  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
344  if (S != MCDisassembler::Success)
345    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
346
347  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
348  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
349  return S;
350}
351
352static DecodeStatus
353Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
354                       const void *Decoder) {
355  unsigned Op1, Op2;
356  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
357  if (S != MCDisassembler::Success)
358    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
359
360  Inst.addOperand(MCOperand::CreateImm(Op1));
361  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
362  return S;
363}
364
365static DecodeStatus
366DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
367                     const void *Decoder) {
368  unsigned Op1, Op2;
369  DecodeStatus S = Decode2OpInstruction(Insn, Op2, Op1);
370  if (S != MCDisassembler::Success)
371    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
372
373  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
374  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
375  return S;
376}
377
378static DecodeStatus
379Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
380                          const void *Decoder) {
381  unsigned Op1, Op2;
382  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
383  if (S != MCDisassembler::Success)
384    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
385
386  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
387  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
388  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
389  return S;
390}
391
392static DecodeStatus
393DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
394                     const void *Decoder) {
395  unsigned Op1, Op2;
396  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
397  if (S != MCDisassembler::Success)
398    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
399
400  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
401  Inst.addOperand(MCOperand::CreateImm(Op2));
402  return S;
403}
404
405static DecodeStatus
406DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
407                         const void *Decoder) {
408  unsigned Op1, Op2;
409  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
410  if (S != MCDisassembler::Success)
411    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
412
413  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
414  DecodeBitpOperand(Inst, Op2, Address, Decoder);
415  return S;
416}
417
418static DecodeStatus
419DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
420                               const void *Decoder) {
421  unsigned Op1, Op2;
422  DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
423  if (S != MCDisassembler::Success)
424    return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
425
426  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
427  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
428  DecodeBitpOperand(Inst, Op2, Address, Decoder);
429  return S;
430}
431
432static DecodeStatus
433DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
434                          const void *Decoder) {
435  // Try and decode as a L3R / L2RUS instruction.
436  unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
437                    fieldFromInstruction(Insn, 27, 5) << 4;
438  switch (Opcode) {
439  case 0x0c:
440    Inst.setOpcode(XCore::STW_l3r);
441    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
442  case 0x1c:
443    Inst.setOpcode(XCore::XOR_l3r);
444    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
445  case 0x2c:
446    Inst.setOpcode(XCore::ASHR_l3r);
447    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
448  case 0x3c:
449    Inst.setOpcode(XCore::LDAWF_l3r);
450    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
451  case 0x4c:
452    Inst.setOpcode(XCore::LDAWB_l3r);
453    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
454  case 0x5c:
455    Inst.setOpcode(XCore::LDA16F_l3r);
456    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
457  case 0x6c:
458    Inst.setOpcode(XCore::LDA16B_l3r);
459    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
460  case 0x7c:
461    Inst.setOpcode(XCore::MUL_l3r);
462    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
463  case 0x8c:
464    Inst.setOpcode(XCore::DIVS_l3r);
465    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
466  case 0x9c:
467    Inst.setOpcode(XCore::DIVU_l3r);
468    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
469  case 0x10c:
470    Inst.setOpcode(XCore::ST16_l3r);
471    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
472  case 0x11c:
473    Inst.setOpcode(XCore::ST8_l3r);
474    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
475  case 0x12c:
476    Inst.setOpcode(XCore::ASHR_l2rus);
477    return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
478  case 0x12d:
479    Inst.setOpcode(XCore::OUTPW_l2rus);
480    return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
481  case 0x12e:
482    Inst.setOpcode(XCore::INPW_l2rus);
483    return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
484  case 0x13c:
485    Inst.setOpcode(XCore::LDAWF_l2rus);
486    return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
487  case 0x14c:
488    Inst.setOpcode(XCore::LDAWB_l2rus);
489    return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
490  case 0x15c:
491    Inst.setOpcode(XCore::CRC_l3r);
492    return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
493  case 0x18c:
494    Inst.setOpcode(XCore::REMS_l3r);
495    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
496  case 0x19c:
497    Inst.setOpcode(XCore::REMU_l3r);
498    return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
499  }
500  return MCDisassembler::Fail;
501}
502
503static DecodeStatus
504DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
505                               const void *Decoder) {
506  unsigned Op1, Op2;
507  DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
508                                        Op1, Op2);
509  if (S != MCDisassembler::Success)
510    return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
511
512  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
513  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
514  return S;
515}
516
517static DecodeStatus
518DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
519                               const void *Decoder) {
520  unsigned Op1, Op2;
521  DecodeStatus S = Decode2OpInstruction(fieldFromInstruction(Insn, 0, 16),
522                                        Op1, Op2);
523  if (S != MCDisassembler::Success)
524    return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
525
526  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
527  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
528  return S;
529}
530
531static DecodeStatus
532Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
533                    const void *Decoder) {
534  unsigned Op1, Op2, Op3;
535  DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
536  if (S == MCDisassembler::Success) {
537    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
538    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
539    DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
540  }
541  return S;
542}
543
544static DecodeStatus
545Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
546                       const void *Decoder) {
547  unsigned Op1, Op2, Op3;
548  DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
549  if (S == MCDisassembler::Success) {
550    Inst.addOperand(MCOperand::CreateImm(Op1));
551    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
552    DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
553  }
554  return S;
555}
556
557static DecodeStatus
558Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
559                      const void *Decoder) {
560  unsigned Op1, Op2, Op3;
561  DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
562  if (S == MCDisassembler::Success) {
563    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
564    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
565    Inst.addOperand(MCOperand::CreateImm(Op3));
566  }
567  return S;
568}
569
570static DecodeStatus
571Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
572                      const void *Decoder) {
573  unsigned Op1, Op2, Op3;
574  DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
575  if (S == MCDisassembler::Success) {
576    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
577    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
578    DecodeBitpOperand(Inst, Op3, Address, Decoder);
579  }
580  return S;
581}
582
583static DecodeStatus
584DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
585                     const void *Decoder) {
586  unsigned Op1, Op2, Op3;
587  DecodeStatus S =
588    Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
589  if (S == MCDisassembler::Success) {
590    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
591    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
592    DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
593  }
594  return S;
595}
596
597static DecodeStatus
598DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
599                           const void *Decoder) {
600  unsigned Op1, Op2, Op3;
601  DecodeStatus S =
602  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
603  if (S == MCDisassembler::Success) {
604    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
605    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
606    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
607    DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
608  }
609  return S;
610}
611
612static DecodeStatus
613DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
614                       const void *Decoder) {
615  unsigned Op1, Op2, Op3;
616  DecodeStatus S =
617  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
618  if (S == MCDisassembler::Success) {
619    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
620    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
621    Inst.addOperand(MCOperand::CreateImm(Op3));
622  }
623  return S;
624}
625
626static DecodeStatus
627DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
628                           const void *Decoder) {
629  unsigned Op1, Op2, Op3;
630  DecodeStatus S =
631  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
632  if (S == MCDisassembler::Success) {
633    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
634    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
635    DecodeBitpOperand(Inst, Op3, Address, Decoder);
636  }
637  return S;
638}
639
640static DecodeStatus
641DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
642                     const void *Decoder) {
643  unsigned Op1, Op2, Op3, Op4, Op5, Op6;
644  DecodeStatus S =
645    Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
646  if (S != MCDisassembler::Success)
647    return S;
648  S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6);
649  if (S != MCDisassembler::Success)
650    return S;
651  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
652  DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
653  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
654  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
655  DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
656  DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
657  return S;
658}
659
660static DecodeStatus
661DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
662                     const void *Decoder) {
663  // Try and decode as a L6R instruction.
664  Inst.clear();
665  unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
666  switch (Opcode) {
667  case 0x00:
668    Inst.setOpcode(XCore::LMUL_l6r);
669    return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
670  }
671  return MCDisassembler::Fail;
672}
673
674static DecodeStatus
675DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
676                     const void *Decoder) {
677  unsigned Op1, Op2, Op3, Op4, Op5;
678  DecodeStatus S =
679    Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
680  if (S != MCDisassembler::Success)
681    return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
682  S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
683  if (S != MCDisassembler::Success)
684    return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
685
686  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
687  DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
688  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
689  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
690  DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
691  return S;
692}
693
694static DecodeStatus
695DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
696                           const void *Decoder) {
697  unsigned Op1, Op2, Op3;
698  unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
699  DecodeStatus S =
700    Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
701  if (S == MCDisassembler::Success) {
702    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
703    S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
704  }
705  if (S == MCDisassembler::Success) {
706    DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
707    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
708    DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
709  }
710  return S;
711}
712
713static DecodeStatus
714DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
715                                 const void *Decoder) {
716  unsigned Op1, Op2, Op3;
717  unsigned Op4 = fieldFromInstruction(Insn, 16, 4);
718  DecodeStatus S =
719  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
720  if (S == MCDisassembler::Success) {
721    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
722    S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
723  }
724  if (S == MCDisassembler::Success) {
725    DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
726    DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
727    DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
728    DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
729  }
730  return S;
731}
732
733MCDisassembler::DecodeStatus
734XCoreDisassembler::getInstruction(MCInst &instr,
735                                  uint64_t &Size,
736                                  const MemoryObject &Region,
737                                  uint64_t Address,
738                                  raw_ostream &vStream,
739                                  raw_ostream &cStream) const {
740  uint16_t insn16;
741
742  if (!readInstruction16(Region, Address, Size, insn16)) {
743    return Fail;
744  }
745
746  // Calling the auto-generated decoder function.
747  DecodeStatus Result = decodeInstruction(DecoderTable16, instr, insn16,
748                                          Address, this, STI);
749  if (Result != Fail) {
750    Size = 2;
751    return Result;
752  }
753
754  uint32_t insn32;
755
756  if (!readInstruction32(Region, Address, Size, insn32)) {
757    return Fail;
758  }
759
760  // Calling the auto-generated decoder function.
761  Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);
762  if (Result != Fail) {
763    Size = 4;
764    return Result;
765  }
766
767  return Fail;
768}
769
770namespace llvm {
771  extern Target TheXCoreTarget;
772}
773
774static MCDisassembler *createXCoreDisassembler(const Target &T,
775                                               const MCSubtargetInfo &STI) {
776  return new XCoreDisassembler(STI, T.createMCRegInfo(""));
777}
778
779extern "C" void LLVMInitializeXCoreDisassembler() {
780  // Register the disassembler.
781  TargetRegistry::RegisterMCDisassembler(TheXCoreTarget,
782                                         createXCoreDisassembler);
783}
784