Cross Reference: /external/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

Lines Matching refs:Inst
87 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
92 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
95 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
98 static DecodeStatus Decode2RInstruction(MCInst &Inst,
103 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
108 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
113 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
118 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
123 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
128 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
133 static DecodeStatus DecodeL2RInstruction(MCInst &Inst,
138 static DecodeStatus DecodeLR2RInstruction(MCInst &Inst,
143 static DecodeStatus Decode3RInstruction(MCInst &Inst,
148 static DecodeStatus Decode3RImmInstruction(MCInst &Inst,
153 static DecodeStatus Decode2RUSInstruction(MCInst &Inst,
158 static DecodeStatus Decode2RUSBitpInstruction(MCInst &Inst,
163 static DecodeStatus DecodeL3RInstruction(MCInst &Inst,
168 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst,
173 static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst,
178 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst,
183 static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
188 static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
193 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst &Inst,
198 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst,
205 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
213   Inst.addOperand(MCOperand::CreateReg(Reg));
217 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
224   Inst.addOperand(MCOperand::CreateImm(Values[Val]));
228 static DecodeStatus DecodeMEMiiOperand(MCInst &Inst, unsigned Val,
230   Inst.addOperand(MCOperand::CreateImm(Val));
231   Inst.addOperand(MCOperand::CreateImm(0));
270 Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
276     Inst.setOpcode(XCore::STW_2rus);
277     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
279     Inst.setOpcode(XCore::LDW_2rus);
280     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
282     Inst.setOpcode(XCore::ADD_3r);
283     return Decode3RInstruction(Inst, Insn, Address, Decoder);
285     Inst.setOpcode(XCore::SUB_3r);
286     return Decode3RInstruction(Inst, Insn, Address, Decoder);
288     Inst.setOpcode(XCore::SHL_3r);
289     return Decode3RInstruction(Inst, Insn, Address, Decoder);
291     Inst.setOpcode(XCore::SHR_3r);
292     return Decode3RInstruction(Inst, Insn, Address, Decoder);
294     Inst.setOpcode(XCore::EQ_3r);
295     return Decode3RInstruction(Inst, Insn, Address, Decoder);
297     Inst.setOpcode(XCore::AND_3r);
298     return Decode3RInstruction(Inst, Insn, Address, Decoder);
300     Inst.setOpcode(XCore::OR_3r);
301     return Decode3RInstruction(Inst, Insn, Address, Decoder);
303     Inst.setOpcode(XCore::LDW_3r);
304     return Decode3RInstruction(Inst, Insn, Address, Decoder);
306     Inst.setOpcode(XCore::LD16S_3r);
307     return Decode3RInstruction(Inst, Insn, Address, Decoder);
309     Inst.setOpcode(XCore::LD8U_3r);
310     return Decode3RInstruction(Inst, Insn, Address, Decoder);
312     Inst.setOpcode(XCore::ADD_2rus);
313     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
315     Inst.setOpcode(XCore::SUB_2rus);
316     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
318     Inst.setOpcode(XCore::SHL_2rus);
319     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
321     Inst.setOpcode(XCore::SHR_2rus);
322     return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
324     Inst.setOpcode(XCore::EQ_2rus);
325     return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
327     Inst.setOpcode(XCore::TSETR_3r);
328     return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
330     Inst.setOpcode(XCore::LSS_3r);
331     return Decode3RInstruction(Inst, Insn, Address, Decoder);
333     Inst.setOpcode(XCore::LSU_3r);
334     return Decode3RInstruction(Inst, Insn, Address, Decoder);
340 Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
345     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
347   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
348   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
353 Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
358     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
360   Inst.addOperand(MCOperand::CreateImm(Op1));
361   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
366 DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
371     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
373   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
374   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
379 Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
384     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
386   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
387   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
388   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
393 DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
398     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
400   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
401   Inst.addOperand(MCOperand::CreateImm(Op2));
406 DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
411     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
413   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
414   DecodeBitpOperand(Inst, Op2, Address, Decoder);
419 DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
424     return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
426   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
427   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
428   DecodeBitpOperand(Inst, Op2, Address, Decoder);
433 DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
440     Inst.setOpcode(XCore::STW_l3r);
441     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
443     Inst.setOpcode(XCore::XOR_l3r);
444     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
446     Inst.setOpcode(XCore::ASHR_l3r);
447     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
449     Inst.setOpcode(XCore::LDAWF_l3r);
450     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
452     Inst.setOpcode(XCore::LDAWB_l3r);
453     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
455     Inst.setOpcode(XCore::LDA16F_l3r);
456     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
458     Inst.setOpcode(XCore::LDA16B_l3r);
459     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
461     Inst.setOpcode(XCore::MUL_l3r);
462     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
464     Inst.setOpcode(XCore::DIVS_l3r);
465     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
467     Inst.setOpcode(XCore::DIVU_l3r);
468     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
470     Inst.setOpcode(XCore::ST16_l3r);
471     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
473     Inst.setOpcode(XCore::ST8_l3r);
474     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
476     Inst.setOpcode(XCore::ASHR_l2rus);
477     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
479     Inst.setOpcode(XCore::OUTPW_l2rus);
480     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
482     Inst.setOpcode(XCore::INPW_l2rus);
483     return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
485     Inst.setOpcode(XCore::LDAWF_l2rus);
486     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
488     Inst.setOpcode(XCore::LDAWB_l2rus);
489     return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
491     Inst.setOpcode(XCore::CRC_l3r);
492     return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
494     Inst.setOpcode(XCore::REMS_l3r);
495     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
497     Inst.setOpcode(XCore::REMU_l3r);
498     return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
504 DecodeL2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
510     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
512   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
513   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
518 DecodeLR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
524     return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
526   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
527   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
532 Decode3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
537     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
538     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
539     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
545 Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
550     Inst.addOperand(MCOperand::CreateImm(Op1));
551     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
552     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
558 Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
563     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
564     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
565     Inst.addOperand(MCOperand::CreateImm(Op3));
571 Decode2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
576     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
577     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
578     DecodeBitpOperand(Inst, Op3, Address, Decoder);
584 DecodeL3RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
590     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
591     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
592     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
598 DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
604     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
605     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
606     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
607     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
613 DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
619     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
620     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
621     Inst.addOperand(MCOperand::CreateImm(Op3));
627 DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
633     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
634     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
635     DecodeBitpOperand(Inst, Op3, Address, Decoder);
641 DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
651   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
652   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
653   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
654   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
655   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
656   DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
661 DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
664   Inst.clear();
668     Inst.setOpcode(XCore::LMUL_l6r);
669     return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
675 DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
681     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
684     return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
686   DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
687   DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
688   DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
689   DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
690   DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
695 DecodeL4RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
702     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
703     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
706     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
707     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
708     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
714 DecodeL4RSrcDstSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
721     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
722     S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
725     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
726     DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
727     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
728     DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);