/external/llvm/lib/MC/MCParser/ |
H A D | COFFAsmParser.cpp | 456 const MCRegisterInfo &MRI = getContext().getRegisterInfo(); local 476 int SEHRegNo = MRI.getSEHRegNum(LLVMRegNo);
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCCodeEmitter.cpp | 476 const MCRegisterInfo &MRI, 475 createAArch64MCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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H A D | AArch64MCTargetDesc.cpp | 105 const MCRegisterInfo &MRI, 108 return new AArch64InstPrinter(MAI, MII, MRI, STI); 101 createAArch64MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCTargetDesc.cpp | 208 const MCRegisterInfo &MRI, 211 return new ARMInstPrinter(MAI, MII, MRI, STI); 204 createARMMCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/ARM/ |
H A D | Thumb1FrameLowering.cpp | 40 const Thumb1RegisterInfo &MRI, 43 MRI, MIFlags); 37 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const TargetInstrInfo &TII, DebugLoc dl, const Thumb1RegisterInfo &MRI, int NumBytes, unsigned MIFlags = MachineInstr::NoFlags) argument
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H A D | Thumb1RegisterInfo.cpp | 96 const ARMBaseRegisterInfo& MRI, 125 MRI.emitLoadConstPool(MBB, MBBI, dl, LdReg, 0, NumBytes, 172 const ARMBaseRegisterInfo& MRI, 231 TII, MRI, MIFlags); 305 const Thumb1RegisterInfo& MRI, 317 emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI); 90 emitThumbRegPlusImmInReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, bool CanChangeCC, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags = MachineInstr::NoFlags) argument 167 emitThumbRegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned BaseReg, int NumBytes, const TargetInstrInfo &TII, const ARMBaseRegisterInfo& MRI, unsigned MIFlags) argument 301 emitThumbConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned DestReg, int Imm, const TargetInstrInfo &TII, const Thumb1RegisterInfo& MRI, DebugLoc dl) argument
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H A D | A15SDOptimizer.cpp | 63 MachineRegisterInfo *MRI; member in struct:__anon9652::A15SDOptimizer 146 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 164 MachineInstr *MI = MRI->getVRegDef(SReg); 230 for (MachineRegisterInfo::use_iterator II = MRI->use_begin(Reg), 231 EE = MRI->use_end(); 263 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg()); 264 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg()); 283 MRI->getRegClass(MI->getOperand(1).getReg()); 284 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 315 MachineInstr *Def = MRI [all...] |
H A D | MLxExpansionPass.cpp | 52 MachineRegisterInfo *MRI; member in struct:__anon9692::MLxExpansion 94 MachineInstr *DefMI = MRI->getVRegDef(Reg); 101 DefMI = MRI->getVRegDef(Reg); 107 DefMI = MRI->getVRegDef(Reg); 119 !MRI->hasOneNonDBGUse(Reg)) 123 MachineInstr *UseMI = &*MRI->use_nodbg_begin(Reg); 130 !MRI->hasOneNonDBGUse(Reg)) 132 UseMI = &*MRI->use_nodbg_begin(Reg); 148 MachineInstr *DefMI = MRI->getVRegDef(Reg); 159 DefMI = MRI [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonNewValueJump.cpp | 232 MachineRegisterInfo &MRI = MF.getRegInfo(); local 234 MachineInstr *def = MRI.getVRegDef(cmpOp2);
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeFrameLowering.cpp | 90 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 92 MachineRegisterInfo::livein_iterator LII = MRI.livein_begin(); 93 MachineRegisterInfo::livein_iterator LIE = MRI.livein_end(); 224 const MachineRegisterInfo &MRI = MF.getRegInfo(); local 250 if (!MRI.isPhysRegUsed(r) && !(isIntr && r == MBlaze::R11)) continue; 292 if (!MRI.isPhysRegUsed(r)) continue;
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/external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
H A D | MBlazeMCCodeEmitter.cpp | 101 const MCRegisterInfo &MRI, 100 createMBlazeMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.h | 81 const MCRegisterInfo &MRI) 82 : MCInstPrinter(MAI, MII, MRI) {} 80 MipsInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 95 const MCRegisterInfo &MRI, 103 const MCRegisterInfo &MRI, 94 createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument 102 createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI, MCContext &Ctx) argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSEFrameLowering.cpp | 275 MachineRegisterInfo &MRI = MF.getRegInfo(); local 281 MRI.setPhysRegUsed(FP);
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H A D | MipsSEISelDAGToDAG.cpp | 39 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI, argument 60 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), 61 E = MRI->use_end(); U != E;) { 172 MachineRegisterInfo *MRI = &MF.getRegInfo(); local 177 replaceUsesWithZeroReg(MRI, *I);
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H A D | MipsSubtarget.h | 101 MipsReginfo MRI; member in class:llvm::MipsSubtarget 157 const MipsReginfo &getMReginfo() const { return MRI; }
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXAsmPrinter.h | 253 const MachineRegisterInfo *MRI; member in class:llvm::NVPTXAsmPrinter
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/external/llvm/lib/Target/R600/ |
H A D | AMDGPUIndirectAddressing.cpp | 37 bool regHasExplicitDef(MachineRegisterInfo &MRI, unsigned Reg) const; 60 MachineRegisterInfo &MRI = MF.getRegInfo(); local 104 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); 119 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); 186 unsigned PhiDstReg = MRI.createVirtualRegister(PhiDstClass); 195 MachineInstr *DefInst = MRI.getVRegDef(Reg); 244 unsigned IndirectReg = MRI.createVirtualRegister(SuperIndirectRegClass); 255 if (regHasExplicitDef(MRI, Reg)) { 292 if (!regHasExplicitDef(MRI, Reg)) { 318 bool AMDGPUIndirectAddressingPass::regHasExplicitDef(MachineRegisterInfo &MRI, argument [all...] |
H A D | AMDGPUInstrInfo.cpp | 250 MachineRegisterInfo &MRI = MF.getRegInfo(); local 258 const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 263 MRI.setRegClass(MO.getReg(), newRegClass);
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H A D | SIInsertWaits.cpp | 51 const MachineRegisterInfo *MRI; member in class:__anon9785::SIInsertWaits 334 MRI = &MF.getRegInfo();
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 212 void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) { argument 215 unsigned SEH = MRI->getEncodingValue(Reg); 216 MRI->mapLLVMRegToSEHReg(Reg, SEH); 376 const MCRegisterInfo &MRI, 379 return new X86ATTInstPrinter(MAI, MII, MRI); 381 return new X86IntelInstPrinter(MAI, MII, MRI); 372 createX86MCInstPrinter(const Target &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI) argument
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/external/llvm/lib/Target/X86/ |
H A D | X86RegisterInfo.cpp | 411 const MachineRegisterInfo *MRI = &MF.getRegInfo(); local 417 if (!MRI->canReserveReg(FramePtr)) 423 return MRI->canReserveReg(BasePtr);
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/external/llvm/lib/CodeGen/ |
H A D | MachineSSAUpdater.cpp | 41 MRI = &MF.getRegInfo(); 57 VRC = MRI->getRegClass(VR); 115 MachineRegisterInfo *MRI, 117 unsigned NewVR = MRI->createVirtualRegister(RC); 151 VRC, MRI, TII); 187 Loc, VRC, MRI, TII); 234 MRI->replaceRegWith(OldReg, NewReg); 298 Updater->VRC, Updater->MRI, 309 Updater->VRC, Updater->MRI, 332 return InstrIsPHI(Updater->MRI 112 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument [all...] |
H A D | MachineSink.cpp | 48 MachineRegisterInfo *MRI; // Machine register information member in class:__anon9488::MachineSinking 132 !MRI->hasOneNonDBGUse(SrcReg)) 135 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 140 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 145 MRI->replaceRegWith(DstReg, SrcReg); 165 if (MRI->use_nodbg_empty(Reg)) 185 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); 199 I = MRI 390 AvoidsSinking(MachineInstr *MI, MachineRegisterInfo *MRI) argument [all...] |
H A D | PHIElimination.cpp | 50 MachineRegisterInfo *MRI; // Machine register information member in class:__anon9494::PHIElimination 127 MRI = &MF.getRegInfo(); 134 MRI->leaveSSA(); 156 if (MRI->use_nodbg_empty(DefReg)) { 199 const MachineRegisterInfo *MRI) { 200 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg), 201 DE = MRI->def_end(); DI != DE; ++DI) 210 const MachineRegisterInfo *MRI) { 212 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI)) 240 if (isSourceDefinedByImplicitDef(MPhi, MRI)) 198 isImplicitlyDefined(unsigned VirtReg, const MachineRegisterInfo *MRI) argument 209 isSourceDefinedByImplicitDef(const MachineInstr *MPhi, const MachineRegisterInfo *MRI) argument [all...] |