/external/clang/lib/StaticAnalyzer/Core/ |
H A D | ProgramState.cpp | 670 if (const MemRegion *Reg = V.getAsRegion()) 671 return isTainted(Reg, Kind); 675 bool ProgramState::isTainted(const MemRegion *Reg, TaintTagType K) const { argument 676 if (!Reg) 681 if (const ElementRegion *ER = dyn_cast<ElementRegion>(Reg)) 684 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) 687 if (const SubRegion *ER = dyn_cast<SubRegion>(Reg)) 732 DynamicTypeInfo ProgramState::getDynamicTypeInfo(const MemRegion *Reg) const { 733 Reg = Reg 752 setDynamicTypeInfo(const MemRegion *Reg, DynamicTypeInfo NewTy) const argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineBasicBlock.h | 294 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); } argument 298 void removeLiveIn(unsigned Reg); 302 bool isLiveIn(unsigned Reg) const; 587 /// computeRegisterLiveness - Return whether (physical) register \c Reg 594 /// \c Reg must be a physical register. 596 unsigned Reg, MachineInstr *MI,
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H A D | MachineFrameInfo.h | 37 unsigned Reg; member in class:llvm::CalleeSavedInfo 42 : Reg(R), FrameIdx(FI) {} 45 unsigned getReg() const { return Reg; }
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H A D | ScheduleDAG.h | 80 /// Reg - For Data, Anti, and Output dependencies, the associated 83 unsigned Reg; member in union:llvm::SDep::__anon9238 106 SDep(SUnit *S, Kind kind, unsigned Reg) argument 110 llvm_unreachable("Reg given for non-register dependence!"); 113 assert(Reg != 0 && 114 "SDep::Anti and SDep::Output must use a non-zero Reg!"); 115 Contents.Reg = Reg; 119 Contents.Reg = Reg; 253 setReg(unsigned Reg) argument [all...] |
H A D | SelectionDAG.h | 433 SDValue getRegister(unsigned Reg, EVT VT); 445 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N) { argument 447 getRegister(Reg, N.getValueType()), N); 453 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, unsigned Reg, SDValue N, argument 456 SDValue Ops[] = { Chain, getRegister(Reg, N.getValueType()), N, Glue }; 460 // Similar to last getCopyToReg() except parameter Reg is a SDValue 461 SDValue getCopyToReg(SDValue Chain, DebugLoc dl, SDValue Reg, SDValue N, argument 464 SDValue Ops[] = { Chain, Reg, N, Glue }; 468 SDValue getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT) { argument 470 SDValue Ops[] = { Chain, getRegister(Reg, V 477 getCopyFromReg(SDValue Chain, DebugLoc dl, unsigned Reg, EVT VT, SDValue Glue) argument [all...] |
/external/llvm/include/llvm/MC/ |
H A D | MCInstrDesc.h | 506 bool hasImplicitUseOfPhysReg(unsigned Reg) const { 509 if (*ImpUses == Reg) return true; 515 bool hasImplicitDefOfPhysReg(unsigned Reg, argument 519 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) 526 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg, argument 530 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg())) 532 return hasImplicitDefOfPhysReg(Reg, &RI);
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 574 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 776 /// FoldImmediate - 'Reg' is known to be defined by a move immediate 779 unsigned Reg, MachineRegisterInfo *MRI) const { 845 /// hasHighOperandLatency - Compute operand latency between a def of 'Reg' 858 /// hasLowDefLatency - Compute operand latency of a def of 'Reg', return true 573 unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, unsigned Reg, bool UnfoldLoad, bool UnfoldStore, SmallVectorImpl<MachineInstr*> &NewMIs) const argument 778 FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI, unsigned Reg, MachineRegisterInfo *MRI) const argument
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/external/llvm/lib/CodeGen/ |
H A D | BranchFolding.cpp | 137 unsigned Reg = I->getOperand(0).getReg(); local 138 ImpDefRegs.insert(Reg); 139 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 155 unsigned Reg = MO.getReg(); local 156 if (ImpDefRegs.count(Reg)) 1486 unsigned Reg = MO.getReg(); local 1487 if (!Reg) 1490 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) 1518 unsigned Reg = MO.getReg(); local 1519 if (!Reg) 1547 unsigned Reg = MO.getReg(); local 1632 unsigned Reg = MO.getReg(); local 1683 unsigned Reg = MO.getReg(); local 1695 unsigned Reg = MO.getReg(); local [all...] |
H A D | InlineSpiller.cpp | 117 SibValueInfo(unsigned Reg, VNInfo *VNI) argument 119 SpillReg(Reg), SpillVNI(VNI), SpillMBB(0), DefMI(0) {} 157 bool isRegToSpill(unsigned Reg) { argument 159 RegsToSpill.end(), Reg) != RegsToSpill.end(); 162 bool isSibling(unsigned Reg); 174 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg); 182 void spillAroundUses(unsigned Reg); 207 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register, 209 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { argument 212 if (MI->getOperand(0).getReg() == Reg) 223 unsigned Reg = Edit->getReg(); local 266 unsigned Reg = Edit->getReg(); local 307 isSibling(unsigned Reg) argument 494 unsigned Reg; local 637 unsigned Reg = RegsToSpill[i]; local 747 unsigned Reg = LI->reg; local 922 unsigned Reg = RegsToSpill[i]; local 934 unsigned Reg = RegsToSpill[i]; local 959 unsigned Reg = RegsToSpill[i-1]; local 979 coalesceStackAccess(MachineInstr *MI, unsigned Reg) argument 1109 spillAroundUses(unsigned Reg) argument [all...] |
H A D | LiveIntervalAnalysis.cpp | 133 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 134 if (hasInterval(Reg)) 135 OS << PrintReg(Reg) << " = " << getInterval(Reg) << '\n'; 175 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 176 if (MRI->reg_nodbg_empty(Reg)) 178 LiveInterval *LI = createInterval(Reg); 179 VirtRegIntervals[Reg] = LI; 248 unsigned Reg = *Supers; local 249 if (!MRI->isReserved(Reg) 511 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 750 unsigned Reg = MO->getReg(); local 974 findLastUseBefore(unsigned Reg) argument 1085 unsigned Reg = OrigRegs[i]; local [all...] |
H A D | MachineBasicBlock.cpp | 328 void MachineBasicBlock::removeLiveIn(unsigned Reg) { argument 330 std::find(LiveIns.begin(), LiveIns.end(), Reg); 335 bool MachineBasicBlock::isLiveIn(unsigned Reg) const { 336 livein_iterator I = std::find(livein_begin(), livein_end(), Reg); 691 unsigned Reg = OI->getReg(); local 692 if (TargetRegisterInfo::isPhysicalRegister(Reg) || 693 LV->getVarInfo(Reg).removeKill(MI)) { 694 KilledRegs.push_back(Reg); 712 unsigned Reg = OI->getReg(); local 713 if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) 782 unsigned Reg = KilledRegs.pop_back_val(); local 819 unsigned Reg = MO.getReg(); local 834 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | MachineLICM.cpp | 177 /// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the 179 void AddToLiveIns(unsigned Reg); 197 /// HasHighOperandLatency - Compute operand latency between a def of 'Reg' 201 unsigned Reg) const; 247 unsigned Reg, unsigned OpIdx, 433 unsigned Reg = MO.getReg(); local 434 if (!Reg) 436 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && 440 if (Reg && (PhysRegDefs.test(Reg) || PhysRegClobber 519 unsigned Reg = *I; local 540 unsigned Reg = MO.getReg(); local 569 unsigned Reg = MO.getReg(); local 586 AddToLiveIns(unsigned Reg) argument 779 getRegisterClassIDAndCost(const MachineInstr *MI, unsigned Reg, unsigned OpIdx, unsigned &RCId, unsigned &RCCost) const argument 817 unsigned Reg = MO.getReg(); local 849 unsigned Reg = MO.getReg(); local 868 unsigned Reg = Defs.pop_back_val(); local 929 unsigned Reg = MO.getReg(); local 978 unsigned Reg = MO->getReg(); local 1055 unsigned Reg = DefMO.getReg(); local 1110 unsigned Reg = MO.getReg(); local 1187 unsigned Reg = MO.getReg(); local 1266 unsigned Reg = MRI->createVirtualRegister(RC); local 1356 unsigned Reg = MI->getOperand(Idx).getReg(); local 1370 unsigned Reg = MI->getOperand(Idx).getReg(); local [all...] |
H A D | MachineVerifier.cpp | 90 // Add Reg and any sub-registers to RV 91 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { argument 92 RV.push_back(Reg); 93 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) 129 bool addPassed(unsigned Reg) { argument 130 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 132 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) 134 return vregsPassed.insert(Reg) 148 addRequired(unsigned Reg) argument 183 isReserved(unsigned Reg) argument 187 isAllocatable(unsigned Reg) argument 845 const unsigned Reg = MO->getReg(); local 974 const unsigned Reg = MO->getReg(); local 1213 unsigned Reg = BBI->getOperand(i).getReg(); local 1285 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 1312 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | ScheduleDAGInstrs.cpp | 213 unsigned Reg = MO.getReg(); local 214 if (Reg == 0) continue; 216 if (TRI->isPhysicalRegister(Reg)) 217 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); 232 unsigned Reg = *I; local 233 if (!Uses.contains(Reg)) 234 Uses.insert(PhysRegSUOper(&ExitSU, -1, Reg)); 307 DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias)); 309 SDep Dep(SU, Kind, /*Reg=*/*Alias); 328 unsigned Reg local 366 unsigned Reg = MI->getOperand(OperIdx).getReg(); local 406 unsigned Reg = MI->getOperand(OperIdx).getReg(); local 760 unsigned Reg = MO.getReg(); local [all...] |
H A D | TwoAddressInstructionPass.cpp | 93 bool sink3AddrInstruction(MachineInstr *MI, unsigned Reg, 96 bool noUseAfterLastDef(unsigned Reg, unsigned Dist, unsigned &LastDef); 110 bool isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI); 114 unsigned Reg); 117 unsigned Reg); 165 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, LiveIntervals *LIS); 211 "Reg should not have empty live interval."); 307 bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg, unsigned Dist, argument 311 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg), 353 static bool isPlainlyKilled(MachineInstr *MI, unsigned Reg, argument 395 isKilled(MachineInstr &MI, unsigned Reg, const MachineRegisterInfo *MRI, const TargetInstrInfo *TII, LiveIntervals *LIS, bool allowFalsePositives) argument 428 isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) argument 448 findOnlyInterestingUse(unsigned Reg, MachineBasicBlock *MBB, MachineRegisterInfo *MRI, const TargetInstrInfo *TII, bool &IsCopy, unsigned &DstReg, bool &IsDstPhys) argument 476 getMappedReg(unsigned Reg, DenseMap<unsigned, unsigned> &RegMap) argument 663 unsigned Reg = DstReg; local 742 rescheduleMIBelowKill(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, unsigned Reg) argument 911 isDefTooClose(unsigned Reg, unsigned Dist, MachineInstr *MI) argument 936 rescheduleKillAboveMI(MachineBasicBlock::iterator &mi, MachineBasicBlock::iterator &nmi, unsigned Reg) argument 1195 unsigned Reg = MRI->createVirtualRegister(RC); local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 162 unsigned Reg = lookUpRegForValue(V); local 163 if (Reg != 0) 164 return Reg; 177 Reg = materializeRegForValue(V, VT); 181 return Reg; 188 unsigned Reg = 0; local 192 Reg = FastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue()); 194 Reg = TargetMaterializeAlloca(cast<AllocaInst>(V)); 198 Reg = 202 Reg 271 UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) argument 616 unsigned Reg = 0; local 760 unsigned Reg = getRegForValue(I->getOperand(0)); local 1065 unsigned Reg = getRegForValue(I->getOperand(0)); local 1494 unsigned Reg = getRegForValue(PHIOp); local [all...] |
H A D | SelectionDAGBuilder.h | 226 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {} 228 /// Reg - the virtual register containing the index of the jump table entry 230 unsigned Reg; member in struct:llvm::SelectionDAGBuilder::JumpTable 268 First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E), 273 unsigned Reg; member in struct:llvm::SelectionDAGBuilder::BitTestBlock 371 void CopyValueToVirtualRegister(const Value *V, unsigned Reg); 460 unsigned Reg,
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/external/llvm/lib/Target/ARM/ |
H A D | ARMFrameLowering.cpp | 85 static bool isCalleeSavedRegister(unsigned Reg, const uint16_t *CSRegs) { argument 87 if (Reg == CSRegs[i]) 174 unsigned Reg = CSI[i].getReg(); local 176 switch (Reg) { 182 if (Reg == FramePtr) 191 if (Reg == FramePtr) 203 if (Reg == ARM::D8) 205 if (Reg < ARM::D8 || Reg >= ARM::D8 + AFI->getNumAlignedDPRCS2Regs()) { 595 unsigned Reg local 666 unsigned Reg = CSI[i-1].getReg(); local 1202 unsigned Reg = CSRegs[i]; local 1314 unsigned Reg = UnspilledCS1GPRs[i]; local 1325 unsigned Reg = UnspilledCS2GPRs.front(); local 1343 unsigned Reg = UnspilledCS1GPRs.back(); local 1355 unsigned Reg = UnspilledCS2GPRs.back(); local [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 84 unsigned &Reg, unsigned &Imm, 409 unsigned Reg = MO.getReg(); local 410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); 413 switch (Reg) { 434 EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, argument 439 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); 739 unsigned Reg, Imm12; local 744 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC. 760 Reg = ARM::PC; 770 isAdd = EncodeAddrModeOpValues(MI, OpIdx, Reg, Imm1 819 unsigned Reg, Imm8; local 860 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg()); local 1117 unsigned Reg, Imm8; local [all...] |
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 668 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); local 669 if (!Reg) return false; 673 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 809 // = Chain, Callee, Reg#1, Reg#2, ... 918 unsigned Reg = MF.addLiveIn(ArgRegEnd, RC); local 919 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 983 unsigned Reg = getMBlazeRegisterFromNumbering(Start); local 984 unsigned LiveReg = MF.addLiveIn(Reg, RC); 1039 unsigned Reg local [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 537 unsigned Reg = CSI[I].getReg(); local 538 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 542 if (PPC::CRBITRCRegClass.contains(Reg)) 548 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 556 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 565 MachineLocation CSSrc(Reg); 876 unsigned Reg = CSI[i].getReg(); local 991 unsigned Reg = CSI[i].getReg(); local 1012 unsigned Reg = CSI[i].getReg(); local 1085 unsigned Reg = CSI[i].getReg(); local 1239 unsigned Reg = CSI[i].getReg(); local [all...] |
H A D | PPCISelDAGToDAG.cpp | 170 /// register can be improved, but it is wrong to substitute Reg+Reg for 171 /// Reg in an asm, because the load or store opcode would have to change. 204 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local 205 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) { 1276 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; local 1279 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
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/external/llvm/lib/Target/R600/ |
H A D | R600ISelLowering.cpp | 330 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local 331 MFI->LiveOuts.push_back(Reg); 332 return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2)); 364 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister(RegIndex); local 365 return CreateLiveInRegister(DAG, &AMDGPU::R600_TReg32RegClass, Reg, VT);
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H A D | R600InstrInfo.cpp | 398 unsigned Reg = MI->getOperand(idx).getReg(); local 399 switch (Reg) { 587 unsigned Reg = AMDGPU::R600_TReg32RegClass.getRegister((4 * Index) + Chan); local 588 Regs.push_back(Reg);
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 57 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 58 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 68 if (unsigned Reg = State.AllocateReg(RegList, 6)) 69 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 120 unsigned Reg = SFI->getSRetReturnReg(); local 121 if (!Reg) 123 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 290 unsigned Reg = SFI->getSRetReturnReg(); local 291 if (!Reg) { 292 Reg 549 unsigned Reg = RegsToPass[i].first; local 576 unsigned Reg = RegsToPass[i].first; local 601 unsigned Reg = RVLocs[i].getLocReg(); local [all...] |